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0e04ce02e6
This clock node is unused, remove it. This allows to fix the following warnings when compiling dtb with W=1 option : arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg): Node /clocks/clockgen-c0 missing or empty reg/ranges property arch/arm/boot/dts/stih410-b2260.dtb: Warning (simple_bus_reg): Node /clocks/clockgen-c0 missing or empty reg/ranges property arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg): Node /clocks/clockgen-c0 missing or empty reg/ranges property Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
327 lines
7.1 KiB
Plaintext
327 lines
7.1 KiB
Plaintext
/*
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* Copyright (C) 2014 STMicroelectronics R&D Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/stih407-clks.h>
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/ {
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* A9 PLL.
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*/
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clockgen-a9@92b0000 {
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compatible = "st,clkgen-c32";
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reg = <0x92b0000 0xffff>;
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clockgen_a9_pll: clockgen-a9-pll {
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#clock-cells = <1>;
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compatible = "st,stih407-clkgen-plla9";
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clocks = <&clk_sysin>;
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clock-output-names = "clockgen-a9-pll-odf";
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};
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};
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/*
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* ARM CPU related clocks.
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*/
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clk_m_a9: clk-m-a9@92b0000 {
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#clock-cells = <0>;
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compatible = "st,stih407-clkgen-a9-mux";
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reg = <0x92b0000 0x10000>;
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clocks = <&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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clockgen-a@90ff000 {
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compatible = "st,clkgen-c32";
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reg = <0x90ff000 0x1000>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll-ofd-0";
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clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
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};
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen";
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#clock-cells = <1>;
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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clock-output-names = "clk-ic-lmi0";
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clock-critical = <CLK_IC_LMI0>;
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};
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};
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clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
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#clock-cells = <1>;
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compatible = "st,quadfs-pll";
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reg = <0x9103000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-fs0-ch0",
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"clk-s-c0-fs0-ch1",
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"clk-s-c0-fs0-ch2",
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"clk-s-c0-fs0-ch3";
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clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
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};
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clk_s_c0: clockgen-c@9103000 {
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compatible = "st,clkgen-c32";
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reg = <0x9103000 0x1000>;
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clk_s_c0_pll0: clk-s-c0-pll0 {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-pll0-odf-0";
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clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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};
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clk_s_c0_pll1: clk-s-c0-pll1 {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll1";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-pll1-odf-0";
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};
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_c0_pll0 0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_quadfs 0>,
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<&clk_s_c0_quadfs 1>,
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<&clk_s_c0_quadfs 2>,
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<&clk_s_c0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-icn-gpu",
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"clk-fdma",
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"clk-nand",
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"clk-hva",
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"clk-proc-stfe",
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"clk-proc-tp",
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"clk-rx-icn-dmu",
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"clk-rx-icn-hva",
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"clk-icn-cpu",
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"clk-tx-icn-dmu",
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"clk-mmc-0",
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"clk-mmc-1",
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"clk-jpegdec",
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"clk-ext2fa9",
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"clk-ic-bdisp-0",
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"clk-ic-bdisp-1",
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"clk-pp-dmu",
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"clk-vid-dmu",
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"clk-dss-lpc",
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"clk-st231-aud-0",
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"clk-st231-gp-1",
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"clk-st231-dmu",
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"clk-icn-lmi",
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"clk-tx-icn-disp-1",
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"clk-icn-sbc",
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"clk-stfe-frc2",
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"clk-eth-phy",
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"clk-eth-ref-phyclk",
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"clk-flash-promip",
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"clk-main-disp",
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"clk-aux-disp",
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"clk-compo-dvp";
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clock-critical = <CLK_PROC_STFE>,
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<CLK_ICN_CPU>,
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<CLK_TX_ICN_DMU>,
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<CLK_EXT2F_A9>,
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<CLK_ICN_LMI>,
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<CLK_ICN_SBC>;
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/*
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* ARM Peripheral clock for timers
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_s_c0_flexgen 13>;
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clock-output-names = "clk-m-a9-ext2f-div2";
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
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#clock-cells = <1>;
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compatible = "st,quadfs";
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reg = <0x9104000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d0-fs0-ch0",
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"clk-s-d0-fs0-ch1",
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"clk-s-d0-fs0-ch2",
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"clk-s-d0-fs0-ch3";
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};
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clockgen-d0@9104000 {
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compatible = "st,clkgen-c32";
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reg = <0x9104000 0x1000>;
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clk_s_d0_flexgen: clk-s-d0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen-audio", "st,flexgen";
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clocks = <&clk_s_d0_quadfs 0>,
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<&clk_s_d0_quadfs 1>,
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<&clk_s_d0_quadfs 2>,
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<&clk_s_d0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-pcm-0",
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"clk-pcm-1",
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"clk-pcm-2",
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"clk-spdiff";
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};
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};
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clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
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#clock-cells = <1>;
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compatible = "st,quadfs";
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reg = <0x9106000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d2-fs0-ch0",
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"clk-s-d2-fs0-ch1",
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"clk-s-d2-fs0-ch2",
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"clk-s-d2-fs0-ch3";
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};
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clockgen-d2@9106000 {
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compatible = "st,clkgen-c32";
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reg = <0x9106000 0x1000>;
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clk_s_d2_flexgen: clk-s-d2-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen-video", "st,flexgen";
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clocks = <&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>,
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<&clk_s_d2_quadfs 2>,
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<&clk_s_d2_quadfs 3>,
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<&clk_sysin>,
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<&clk_sysin>,
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<&clk_tmdsout_hdmi>;
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clock-output-names = "clk-pix-main-disp",
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"clk-pix-pip",
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"clk-pix-gdp1",
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"clk-pix-gdp2",
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"clk-pix-gdp3",
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"clk-pix-gdp4",
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"clk-pix-aux-disp",
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"clk-denc",
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"clk-pix-hddac",
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"clk-hddac",
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"clk-sddac",
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"clk-pix-dvo",
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"clk-dvo",
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"clk-pix-hdmi",
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"clk-tmds-hdmi",
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"clk-ref-hdmiphy";
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};
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};
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clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
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#clock-cells = <1>;
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compatible = "st,quadfs";
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reg = <0x9107000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d3-fs0-ch0",
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"clk-s-d3-fs0-ch1",
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"clk-s-d3-fs0-ch2",
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"clk-s-d3-fs0-ch3";
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};
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clockgen-d3@9107000 {
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compatible = "st,clkgen-c32";
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reg = <0x9107000 0x1000>;
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clk_s_d3_flexgen: clk-s-d3-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_d3_quadfs 0>,
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<&clk_s_d3_quadfs 1>,
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<&clk_s_d3_quadfs 2>,
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<&clk_s_d3_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-stfe-frc1",
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"clk-tsout-0",
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"clk-tsout-1",
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"clk-mchi",
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"clk-vsens-compo",
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"clk-frc1-remote",
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"clk-lpc-0",
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"clk-lpc-1";
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};
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};
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};
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};
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