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672e60b72b
The Coreboot version on veyron ChromeOS devices seems to ignore
memory@0 nodes when updating the available memory and instead
inserts another memory node without the address.
This leads to 4GB systems only ever be using 2GB as the memory@0
node takes precedence. So remove the @0 for veyron devices.
Fixes: 0b639b815f ("ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards")
Cc: stable@vger.kernel.org
Reported-by: Heikki Lindholm <holin@iki.fi>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
552 lines
12 KiB
Plaintext
552 lines
12 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron (and derivatives) board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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#include <dt-bindings/clock/rockchip,rk808.h>
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#include <dt-bindings/input/input.h>
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#include "rk3288.dtsi"
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/ {
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/*
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* The default coreboot on veyron devices ignores memory@0 nodes
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* and would instead create another memory node.
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*/
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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gpio_keys: gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_key_l>;
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power {
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label = "Power";
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gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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debounce-interval = <100>;
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wakeup-source;
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};
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&ap_warm_reset_h>;
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priority = <200>;
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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pinctrl-0 = <&emmc_reset>;
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pinctrl-names = "default";
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reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&rk808 RK808_CLKOUT1>;
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clock-names = "ext_clock";
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pinctrl-names = "default";
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pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
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/*
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* On the module itself this is one of these (depending
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* on the actual card populated):
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* - SDIO_RESET_L_WL_REG_ON
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* - PDN (power down when low)
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*/
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reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
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};
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vcc_5v: vcc-5v {
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compatible = "regulator-fixed";
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regulator-name = "vcc_5v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vcc33_sys: vcc33-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc33_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vcc50_hdmi: vcc50-hdmi {
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compatible = "regulator-fixed";
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regulator-name = "vcc50_hdmi";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_5v>;
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};
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};
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&cpu0 {
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cpu0-supply = <&vdd_cpu>;
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};
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/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
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&cpu_opp_table {
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/delete-node/ opp-312000000;
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opp-1512000000 {
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opp-microvolt = <1250000>;
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};
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opp-1608000000 {
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opp-microvolt = <1300000>;
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};
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opp-1704000000 {
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opp-hz = /bits/ 64 <1704000000>;
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opp-microvolt = <1350000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1400000>;
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};
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};
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&emmc {
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status = "okay";
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bus-width = <8>;
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cap-mmc-highspeed;
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rockchip,default-sample-phase = <158>;
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disable-wp;
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mmc-hs200-1_8v;
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mmc-pwrseq = <&emmc_pwrseq>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
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};
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&gpu {
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mali-supply = <&vdd_gpu>;
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status = "okay";
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};
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&hdmi {
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ddc-i2c-bus = <&i2c5>;
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
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i2c-scl-rising-time-ns = <100>; /* 45ns measured */
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rk808: pmic@1b {
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compatible = "rockchip,rk808";
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reg = <0x1b>;
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clock-output-names = "xin32k", "wifibt_32kin";
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interrupt-parent = <&gpio0>;
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interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l>;
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rockchip,system-power-controller;
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wakeup-source;
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#clock-cells = <1>;
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vcc1-supply = <&vcc33_sys>;
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vcc2-supply = <&vcc33_sys>;
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vcc3-supply = <&vcc33_sys>;
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vcc4-supply = <&vcc33_sys>;
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vcc6-supply = <&vcc_5v>;
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vcc7-supply = <&vcc33_sys>;
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vcc8-supply = <&vcc33_sys>;
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vcc12-supply = <&vcc_18>;
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vddio-supply = <&vcc33_io>;
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regulators {
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vdd_cpu: DCDC_REG1 {
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regulator-name = "vdd_arm";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <1450000>;
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regulator-ramp-delay = <6001>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_gpu: DCDC_REG2 {
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regulator-name = "vdd_gpu";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1250000>;
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regulator-ramp-delay = <6001>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1000000>;
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};
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};
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vcc135_ddr: DCDC_REG3 {
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regulator-name = "vcc135_ddr";
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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};
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/*
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* vcc_18 has several aliases. (vcc18_flashio and
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* vcc18_wl). We'll add those aliases here just to
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* make it easier to follow the schematic. The signals
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* are actually hooked together and only separated for
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* power measurement purposes).
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*/
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vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
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regulator-name = "vcc_18";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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/*
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* Note that both vcc33_io and vcc33_pmuio are always
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* powered together. To simplify the logic in the dts
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* we just refer to vcc33_io every time something is
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* powered from vcc33_pmuio. In fact, on later boards
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* (such as danger) they're the same net.
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*/
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vcc33_io: LDO_REG1 {
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regulator-name = "vcc33_io";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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};
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};
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vdd_10: LDO_REG3 {
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regulator-name = "vdd_10";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1000000>;
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};
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};
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vdd10_lcd_pwren_h: LDO_REG7 {
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regulator-name = "vdd10_lcd_pwren_h";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc33_lcd: SWITCH_REG1 {
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regulator-name = "vcc33_lcd";
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
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i2c-scl-rising-time-ns = <100>; /* 40ns measured */
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tpm: tpm@20 {
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compatible = "infineon,slb9645tt";
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reg = <0x20>;
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powered-while-suspended;
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};
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};
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&i2c2 {
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status = "okay";
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/* 100kHz since 4.7k resistors don't rise fast enough */
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clock-frequency = <100000>;
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i2c-scl-falling-time-ns = <50>; /* 10ns measured */
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i2c-scl-rising-time-ns = <800>; /* 600ns measured */
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};
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&i2c4 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-scl-falling-time-ns = <50>; /* 11ns measured */
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i2c-scl-rising-time-ns = <300>; /* 225ns measured */
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};
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&i2c5 {
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status = "okay";
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clock-frequency = <100000>;
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i2c-scl-falling-time-ns = <300>;
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i2c-scl-rising-time-ns = <1000>;
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};
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&io_domains {
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status = "okay";
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bb-supply = <&vcc33_io>;
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dvp-supply = <&vcc_18>;
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flash0-supply = <&vcc18_flashio>;
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gpio1830-supply = <&vcc33_io>;
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gpio30-supply = <&vcc33_io>;
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lcdc-supply = <&vcc33_lcd>;
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wifi-supply = <&vcc18_wl>;
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};
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&pwm1 {
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status = "okay";
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};
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&sdio0 {
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status = "okay";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-sdio-irq;
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keep-power-in-suspend;
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mmc-pwrseq = <&sdio_pwrseq>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc33_sys>;
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vqmmc-supply = <&vcc18_wl>;
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};
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&spi2 {
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status = "okay";
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rx-sample-delay-ns = <12>;
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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&tsadc {
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status = "okay";
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rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
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rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
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};
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&uart0 {
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status = "okay";
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/* We need to go faster than 24MHz, so adjust clock parents / rates */
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assigned-clocks = <&cru SCLK_UART0>;
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assigned-clock-rates = <48000000>;
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/* Pins don't include flow control by default; add that in */
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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};
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&uart1 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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&usb_host0_ehci {
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status = "okay";
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needs-reset-on-resume;
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};
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&usb_host1 {
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status = "okay";
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};
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&usb_otg {
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status = "okay";
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assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
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assigned-clock-parents = <&usbphy0>;
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dr_mode = "host";
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};
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&vopb {
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status = "okay";
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};
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&vopb_mmu {
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status = "okay";
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};
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&wdt {
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status = "okay";
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};
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&pinctrl {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <
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/* Common for sleep and wake, but no owners */
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&global_pwroff
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>;
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pinctrl-1 = <
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/* Common for sleep and wake, but no owners */
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&global_pwroff
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>;
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pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
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bias-disable;
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drive-strength = <8>;
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};
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pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
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bias-pull-up;
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drive-strength = <8>;
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};
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pcfg_output_high: pcfg-output-high {
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output-high;
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};
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pcfg_output_low: pcfg-output-low {
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output-low;
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};
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buttons {
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pwr_key_l: pwr-key-l {
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rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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emmc {
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emmc_reset: emmc-reset {
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rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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/*
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* We run eMMC at max speed; bump up drive strength.
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* We also have external pulls, so disable the internal ones.
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*/
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emmc_clk: emmc-clk {
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rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
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};
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emmc_bus8: emmc-bus8 {
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rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
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<3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
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<3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
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<3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
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<3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
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<3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
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<3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
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<3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
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};
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};
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pmic {
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pmic_int_l: pmic-int-l {
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rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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reboot {
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ap_warm_reset_h: ap-warm-reset-h {
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rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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recovery-switch {
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rec_mode_l: rec-mode-l {
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rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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sdio0 {
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wifi_enable_h: wifienable-h {
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rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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/* NOTE: mislabelled on schematic; should be bt_enable_h */
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bt_enable_l: bt-enable-l {
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rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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/*
|
|
* We run sdio0 at max speed; bump up drive strength.
|
|
* We also have external pulls, so disable the internal ones.
|
|
*/
|
|
sdio0_bus4: sdio0-bus4 {
|
|
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
sdio0_cmd: sdio0-cmd {
|
|
rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
sdio0_clk: sdio0-clk {
|
|
rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
};
|
|
|
|
tpm {
|
|
tpm_int_h: tpm-int-h {
|
|
rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
write-protect {
|
|
fw_wp_ap: fw-wp-ap {
|
|
rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|