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c8c23423cc
The DCP block on 6ull has no major differences other than requiring explicit clock enabling. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
70 lines
1.5 KiB
Plaintext
70 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Copyright 2016 Freescale Semiconductor, Inc.
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#include "imx6ul.dtsi"
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#include "imx6ull-pinfunc.h"
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#include "imx6ull-pinfunc-snvs.h"
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/* Delete UART8 in AIPS-1 (i.MX6UL specific) */
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/delete-node/ &uart8;
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/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */
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/delete-node/ &crypto;
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&cpu0 {
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operating-points = <
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/* kHz uV */
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900000 1275000
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792000 1225000
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528000 1175000
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396000 1025000
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198000 950000
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>;
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fsl,soc-operating-points = <
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/* KHz uV */
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900000 1250000
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792000 1175000
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528000 1175000
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396000 1175000
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198000 1175000
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>;
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};
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/ {
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soc {
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aips3: aips-bus@2200000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02200000 0x100000>;
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ranges;
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dcp: crypto@2280000 {
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compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";
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reg = <0x02280000 0x4000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
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clock-names = "dcp";
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};
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iomuxc_snvs: iomuxc-snvs@2290000 {
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compatible = "fsl,imx6ull-iomuxc-snvs";
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reg = <0x02290000 0x4000>;
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};
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uart8: serial@2288000 {
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compatible = "fsl,imx6ul-uart",
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"fsl,imx6q-uart";
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reg = <0x02288000 0x4000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_UART8_IPG>,
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<&clks IMX6UL_CLK_UART8_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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};
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};
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