Boris Brezillon 64c160f322 mtd: spi-nor: Create a ->set_4byte() method ... The procedure used to enable 4 byte addressing mode depends on the NOR device, so let's provide a hook so that manufacturer specific handling can be implemented in a sane way. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [tudor.ambarus@microchip.com: use nor->params.set_4byte() instead of nor->set_4byte()] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>		2019-08-28 12:40:28 +03:00
..
aspeed-smc.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152	2019-05-30 11:26:32 -07:00
cadence-quadspi.c	mtd: spi-nor: Fix Cadence QSPI RCU Schedule Stall	2019-08-21 10:07:42 +03:00
hisi-sfc.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13	2019-05-21 11:28:45 +02:00
intel-spi-pci.c	mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake SPI serial flash	2019-08-20 17:47:18 +03:00
intel-spi-platform.c	mtd: spi-nor: intel-spi: Convert to use SPDX identifier	2019-06-22 14:59:27 +03:00
intel-spi.c	mtd: spi-nor: intel-spi: Whitelist 4B read commands	2019-08-21 11:09:46 +03:00
intel-spi.h	mtd: spi-nor: intel-spi: Convert to use SPDX identifier	2019-06-22 14:59:27 +03:00
Kconfig	mtd: spi-nor: Move m25p80 code in spi-nor.c	2019-08-12 10:54:12 +03:00
Makefile	mtd: spi-nor: stm32: remove the driver as it was replaced by spi-stm32-qspi.c	2019-06-07 07:10:38 +03:00
mtk-quadspi.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
nxp-spifi.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
spi-nor.c	mtd: spi-nor: Create a ->set_4byte() method	2019-08-28 12:40:28 +03:00