Chen Lu 64a19591a2 riscv: fix misalgned trap vector base address ... The trap vector marked by label .Lsecondary_park must align on a 4-byte boundary, as the {m,s}tvec is defined to require 4-byte alignment. Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn> Reviewed-by: Anup Patel <anup.patel@wdc.com> Fixes: e011995e82 ("RISC-V: Move relocate and few other functions out of __init") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-10-27 13:08:01 -07:00
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boot	riscv: dts: microchip: mpfs-icicle: Fix serial console	2021-09-10 23:58:19 -07:00
configs	riscv: defconfig: enable NLS_CODEPAGE_437, NLS_ISO8859_1	2021-09-10 21:31:12 -07:00
errata	riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled	2021-06-01 21:16:41 -07:00
include	Merge remote-tracking branch 'palmer/riscv-clone3' into fixes	2021-10-04 16:02:04 -07:00
kernel	riscv: fix misalgned trap vector base address	2021-10-27 13:08:01 -07:00
lib	riscv: __asm_copy_to-from_user: Fix: Typos in comments	2021-07-23 17:49:12 -07:00
mm	riscv: Flush current cpu icache before other cpus	2021-10-04 18:24:15 -07:00
net	bpf: Introduce BPF nospec instruction for mitigating Spectre v4	2021-07-29 00:20:56 +02:00
Kbuild	riscv: Allow device trees to be built into the kernel	2020-05-18 11:38:05 -07:00
Kconfig	RISC-V Patches for the 5.15 Merge Window, Part 2	2021-09-11 14:29:42 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.erratas	riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y	2021-05-06 09:40:13 -07:00
Kconfig.socs	riscv: sifive: fix Kconfig errata warning	2021-06-12 17:20:50 -07:00
Makefile	riscv: move the (z)install rules to arch/riscv/Makefile	2021-09-10 23:08:26 -07:00