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a5cf68b04b
The point is to share more code between the PFB/PGRAPH tile region hooks, and give the hardware specific functions a chance to allocate per-region resources. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
117 lines
3.2 KiB
C
117 lines
3.2 KiB
C
/*
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* Copyright (C) 2010 Francisco Jerez.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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void
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nv30_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
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uint32_t size, uint32_t pitch, uint32_t flags)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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tile->addr = addr | 1;
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tile->limit = max(1u, addr + size) - 1;
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tile->pitch = pitch;
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}
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void
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nv30_fb_free_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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tile->addr = tile->limit = tile->pitch = 0;
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}
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static int
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calc_bias(struct drm_device *dev, int k, int i, int j)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int b = (dev_priv->chipset > 0x30 ?
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nv_rd32(dev, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
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0) & 0xf;
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return 2 * (b & 0x8 ? b - 0x10 : b);
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}
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static int
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calc_ref(struct drm_device *dev, int l, int k, int i)
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{
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int j, x = 0;
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for (j = 0; j < 4; j++) {
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int m = (l >> (8 * i) & 0xff) + calc_bias(dev, k, i, j);
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x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j);
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}
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return x;
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}
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int
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nv30_fb_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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int i, j;
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pfb->num_tiles = NV10_PFB_TILE__SIZE;
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/* Turn all the tiling regions off. */
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for (i = 0; i < pfb->num_tiles; i++)
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pfb->set_tile_region(dev, i);
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/* Init the memory timing regs at 0x10037c/0x1003ac */
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if (dev_priv->chipset == 0x30 ||
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dev_priv->chipset == 0x31 ||
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dev_priv->chipset == 0x35) {
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/* Related to ROP count */
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int n = (dev_priv->chipset == 0x31 ? 2 : 4);
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int l = nv_rd32(dev, 0x1003d0);
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for (i = 0; i < n; i++) {
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for (j = 0; j < 3; j++)
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nv_wr32(dev, 0x10037c + 0xc * i + 0x4 * j,
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calc_ref(dev, l, 0, j));
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for (j = 0; j < 2; j++)
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nv_wr32(dev, 0x1003ac + 0x8 * i + 0x4 * j,
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calc_ref(dev, l, 1, j));
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}
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}
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return 0;
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}
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void
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nv30_fb_takedown(struct drm_device *dev)
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{
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}
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