mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-28 21:45:01 +08:00
467f4bd260
Looks like we're missing few entries for omap2 and the drivers have only worked because of the omap hwmod building the devices for the missing entries. Let's fix the missing entries so we don't need to rely on hwmod for the basic data and can then later on remove the duplicate data from hwmod. Otherwise device tree only drivers will not work properly. Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: devicetree@vger.kernel.org Signed-off-by: Tony Lindgren <tony@atomide.com>
276 lines
5.7 KiB
Plaintext
276 lines
5.7 KiB
Plaintext
/*
|
|
* Device Tree Source for OMAP2 SoC
|
|
*
|
|
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public License
|
|
* version 2. This program is licensed "as is" without any warranty of any
|
|
* kind, whether express or implied.
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/pinctrl/omap.h>
|
|
|
|
#include "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
|
|
interrupt-parent = <&intc>;
|
|
|
|
aliases {
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
i2c0 = &i2c1;
|
|
i2c1 = &i2c2;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
|
|
cpu {
|
|
compatible = "arm,arm1136jf-s";
|
|
device_type = "cpu";
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,arm1136-pmu";
|
|
interrupts = <3>;
|
|
};
|
|
|
|
soc {
|
|
compatible = "ti,omap-infra";
|
|
mpu {
|
|
compatible = "ti,omap2-mpu";
|
|
ti,hwmods = "mpu";
|
|
};
|
|
};
|
|
|
|
ocp {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "l3_main";
|
|
|
|
aes: aes@480a6000 {
|
|
compatible = "ti,omap2-aes";
|
|
ti,hwmods = "aes";
|
|
reg = <0x480a6000 0x50>;
|
|
dmas = <&sdma 9 &sdma 10>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
hdq1w: 1w@480b2000 {
|
|
compatible = "ti,omap2420-1w";
|
|
ti,hwmods = "hdq1w";
|
|
reg = <0x480b2000 0x1000>;
|
|
interrupts = <58>;
|
|
};
|
|
|
|
mailbox: mailbox@48094000 {
|
|
compatible = "ti,omap2-mailbox";
|
|
ti,hwmods = "mailbox";
|
|
reg = <0x48094000 0x200>;
|
|
interrupts = <26>;
|
|
};
|
|
|
|
intc: interrupt-controller@1 {
|
|
compatible = "ti,omap2-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
ti,intc-size = <96>;
|
|
reg = <0x480FE000 0x1000>;
|
|
};
|
|
|
|
sdma: dma-controller@48056000 {
|
|
compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
|
|
ti,hwmods = "dma";
|
|
reg = <0x48056000 0x1000>;
|
|
interrupts = <12>,
|
|
<13>,
|
|
<14>,
|
|
<15>;
|
|
#dma-cells = <1>;
|
|
#dma-channels = <32>;
|
|
#dma-requests = <64>;
|
|
};
|
|
|
|
i2c1: i2c@48070000 {
|
|
compatible = "ti,omap2-i2c";
|
|
ti,hwmods = "i2c1";
|
|
reg = <0x48070000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <56>;
|
|
dmas = <&sdma 27 &sdma 28>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
i2c2: i2c@48072000 {
|
|
compatible = "ti,omap2-i2c";
|
|
ti,hwmods = "i2c2";
|
|
reg = <0x48072000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <57>;
|
|
dmas = <&sdma 29 &sdma 30>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
mcspi1: mcspi@48098000 {
|
|
compatible = "ti,omap2-mcspi";
|
|
ti,hwmods = "mcspi1";
|
|
reg = <0x48098000 0x100>;
|
|
interrupts = <65>;
|
|
dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
|
|
&sdma 39 &sdma 40 &sdma 41 &sdma 42>;
|
|
dma-names = "tx0", "rx0", "tx1", "rx1",
|
|
"tx2", "rx2", "tx3", "rx3";
|
|
};
|
|
|
|
mcspi2: mcspi@4809a000 {
|
|
compatible = "ti,omap2-mcspi";
|
|
ti,hwmods = "mcspi2";
|
|
reg = <0x4809a000 0x100>;
|
|
interrupts = <66>;
|
|
dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
|
|
dma-names = "tx0", "rx0", "tx1", "rx1";
|
|
};
|
|
|
|
rng: rng@480a0000 {
|
|
compatible = "ti,omap2-rng";
|
|
ti,hwmods = "rng";
|
|
reg = <0x480a0000 0x50>;
|
|
interrupts = <36>;
|
|
};
|
|
|
|
sham: sham@480a4000 {
|
|
compatible = "ti,omap2-sham";
|
|
ti,hwmods = "sham";
|
|
reg = <0x480a4000 0x64>;
|
|
interrupts = <51>;
|
|
dmas = <&sdma 13>;
|
|
dma-names = "rx";
|
|
};
|
|
|
|
uart1: serial@4806a000 {
|
|
compatible = "ti,omap2-uart";
|
|
ti,hwmods = "uart1";
|
|
reg = <0x4806a000 0x2000>;
|
|
interrupts = <72>;
|
|
dmas = <&sdma 49 &sdma 50>;
|
|
dma-names = "tx", "rx";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart2: serial@4806c000 {
|
|
compatible = "ti,omap2-uart";
|
|
ti,hwmods = "uart2";
|
|
reg = <0x4806c000 0x400>;
|
|
interrupts = <73>;
|
|
dmas = <&sdma 51 &sdma 52>;
|
|
dma-names = "tx", "rx";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart3: serial@4806e000 {
|
|
compatible = "ti,omap2-uart";
|
|
ti,hwmods = "uart3";
|
|
reg = <0x4806e000 0x400>;
|
|
interrupts = <74>;
|
|
dmas = <&sdma 53 &sdma 54>;
|
|
dma-names = "tx", "rx";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
timer2: timer@4802a000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x4802a000 0x400>;
|
|
interrupts = <38>;
|
|
ti,hwmods = "timer2";
|
|
};
|
|
|
|
timer3: timer@48078000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x48078000 0x400>;
|
|
interrupts = <39>;
|
|
ti,hwmods = "timer3";
|
|
};
|
|
|
|
timer4: timer@4807a000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x4807a000 0x400>;
|
|
interrupts = <40>;
|
|
ti,hwmods = "timer4";
|
|
};
|
|
|
|
timer5: timer@4807c000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x4807c000 0x400>;
|
|
interrupts = <41>;
|
|
ti,hwmods = "timer5";
|
|
ti,timer-dsp;
|
|
};
|
|
|
|
timer6: timer@4807e000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x4807e000 0x400>;
|
|
interrupts = <42>;
|
|
ti,hwmods = "timer6";
|
|
ti,timer-dsp;
|
|
};
|
|
|
|
timer7: timer@48080000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x48080000 0x400>;
|
|
interrupts = <43>;
|
|
ti,hwmods = "timer7";
|
|
ti,timer-dsp;
|
|
};
|
|
|
|
timer8: timer@48082000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x48082000 0x400>;
|
|
interrupts = <44>;
|
|
ti,hwmods = "timer8";
|
|
ti,timer-dsp;
|
|
};
|
|
|
|
timer9: timer@48084000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x48084000 0x400>;
|
|
interrupts = <45>;
|
|
ti,hwmods = "timer9";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer10: timer@48086000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x48086000 0x400>;
|
|
interrupts = <46>;
|
|
ti,hwmods = "timer10";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer11: timer@48088000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x48088000 0x400>;
|
|
interrupts = <47>;
|
|
ti,hwmods = "timer11";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer12: timer@4808a000 {
|
|
compatible = "ti,omap2420-timer";
|
|
reg = <0x4808a000 0x400>;
|
|
interrupts = <48>;
|
|
ti,hwmods = "timer12";
|
|
ti,timer-pwm;
|
|
};
|
|
};
|
|
};
|