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a47e5bb576
Compiling with GCC 4.8 yields several instances of
crypto/vmac.c: In function ‘vmac_final’:
crypto/vmac.c:616:9: warning: value computed is not used [-Wunused-value]
memset(&mac, 0, sizeof(vmac_t));
^
arch/alpha/include/asm/string.h:31:25: note: in definition of macro ‘memset’
? __builtin_memset((s),0,(n)) \
^
Converting the macro to an inline function eliminates this problem.
However, doing only that causes problems with the GCC 3.x series. The
inline function cannot be named "memset", as otherwise we wind up with
recursion via __builtin_memset. Solve this by adjusting the symbols
such that __memset is the inline, and ___memset is the real function.
Signed-off-by: Richard Henderson <rth@twiddle.net>
128 lines
2.9 KiB
ArmAsm
128 lines
2.9 KiB
ArmAsm
/*
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* linux/arch/alpha/lib/memset.S
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*
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* This is an efficient (and small) implementation of the C library "memset()"
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* function for the alpha.
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*
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* (C) Copyright 1996 Linus Torvalds
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*
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* This routine is "moral-ware": you are free to use it any way you wish, and
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* the only obligation I put on you is a moral one: if you make any improvements
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* to the routine, please send me your improvements for me to use similarly.
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*
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* The scheduling comments are according to the EV5 documentation (and done by
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* hand, so they might well be incorrect, please do tell me about it..)
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*/
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.set noat
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.set noreorder
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.text
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.globl memset
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.globl __memset
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.globl ___memset
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.globl __memsetw
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.globl __constant_c_memset
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.ent ___memset
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.align 5
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___memset:
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.frame $30,0,$26,0
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.prologue 0
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and $17,255,$1 /* E1 */
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insbl $17,1,$17 /* .. E0 */
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bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
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sll $17,16,$1 /* E1 (p-c latency, next cycle) */
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bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
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sll $17,32,$1 /* E1 (p-c latency, next cycle) */
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bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
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ldq_u $31,0($30) /* .. E1 */
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.align 5
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__constant_c_memset:
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addq $18,$16,$6 /* E0 */
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bis $16,$16,$0 /* .. E1 */
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xor $16,$6,$1 /* E0 */
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ble $18,end /* .. E1 */
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bic $1,7,$1 /* E0 */
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beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
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and $16,7,$3 /* E0 */
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beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
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ldq_u $4,0($16) /* E0 */
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bis $16,$16,$5 /* .. E1 */
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insql $17,$16,$2 /* E0 */
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subq $3,8,$3 /* .. E1 */
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addq $18,$3,$18 /* E0 $18 is new count ($3 is negative) */
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mskql $4,$16,$4 /* .. E1 (and possible load stall) */
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subq $16,$3,$16 /* E0 $16 is new aligned destination */
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bis $2,$4,$1 /* .. E1 */
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bis $31,$31,$31 /* E0 */
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ldq_u $31,0($30) /* .. E1 */
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stq_u $1,0($5) /* E0 */
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bis $31,$31,$31 /* .. E1 */
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.align 4
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aligned:
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sra $18,3,$3 /* E0 */
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and $18,7,$18 /* .. E1 */
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bis $16,$16,$5 /* E0 */
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beq $3,no_quad /* .. E1 */
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.align 3
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loop:
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stq $17,0($5) /* E0 */
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subq $3,1,$3 /* .. E1 */
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addq $5,8,$5 /* E0 */
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bne $3,loop /* .. E1 */
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no_quad:
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bis $31,$31,$31 /* E0 */
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beq $18,end /* .. E1 */
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ldq $7,0($5) /* E0 */
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mskqh $7,$6,$2 /* .. E1 (and load stall) */
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insqh $17,$6,$4 /* E0 */
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bis $2,$4,$1 /* .. E1 */
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stq $1,0($5) /* E0 */
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ret $31,($26),1 /* .. E1 */
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.align 3
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within_one_quad:
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ldq_u $1,0($16) /* E0 */
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insql $17,$16,$2 /* E1 */
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mskql $1,$16,$4 /* E0 (after load stall) */
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bis $2,$4,$2 /* E0 */
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mskql $2,$6,$4 /* E0 */
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mskqh $1,$6,$2 /* .. E1 */
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bis $2,$4,$1 /* E0 */
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stq_u $1,0($16) /* E0 */
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end:
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ret $31,($26),1 /* E1 */
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.end ___memset
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.align 5
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.ent __memsetw
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__memsetw:
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.prologue 0
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inswl $17,0,$1 /* E0 */
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inswl $17,2,$2 /* E0 */
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inswl $17,4,$3 /* E0 */
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or $1,$2,$1 /* .. E1 */
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inswl $17,6,$4 /* E0 */
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or $1,$3,$1 /* .. E1 */
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or $1,$4,$17 /* E0 */
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br __constant_c_memset /* .. E1 */
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.end __memsetw
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memset = ___memset
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__memset = ___memset
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