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5fb6e8cf53
The generic atomic64 implementation provides:
* atomic64_and_return()
* atomic64_or_return()
* atomic64_xor_return()
... but none of these exist in the standard atomic64 API as described by
scripts/atomic/atomics.tbl, and none of these have prototypes exposed by
<asm-generic/atomic64.h>.
The lkp kernel test robot noted this results in warnings when building with
W=1:
lib/atomic64.c:82:5: warning: no previous prototype for 'generic_atomic64_and_return' [-Wmissing-prototypes]
lib/atomic64.c:82:5: warning: no previous prototype for 'generic_atomic64_or_return' [-Wmissing-prototypes]
lib/atomic64.c:82:5: warning: no previous prototype for 'generic_atomic64_xor_return' [-Wmissing-prototypes]
This appears to have been a thinko in commit:
28aa2bda22 ("locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()")
... where we grouped add/sub separately from and/ox/xor, so that we could avoid
implementing _return forms for the latter group, but forgot to remove
ATOMIC64_OP_RETURN() for that group.
This doesn't cause any functional problem, but it's pointless to build code
which cannot be used. Remove the unusable code. This does not affect add/sub,
for which _return forms will still be built.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Boqun Feng <boqun.feng@gmail.com>
Link: https://lore.kernel.org/r/20211126115923.41489-1-mark.rutland@arm.com
190 lines
4.5 KiB
C
190 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Generic implementation of 64-bit atomics using spinlocks,
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* useful on processors that don't have 64-bit atomic instructions.
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*
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* Copyright © 2009 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/cache.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/atomic.h>
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/*
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* We use a hashed array of spinlocks to provide exclusive access
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* to each atomic64_t variable. Since this is expected to used on
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* systems with small numbers of CPUs (<= 4 or so), we use a
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* relatively small array of 16 spinlocks to avoid wasting too much
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* memory on the spinlock array.
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*/
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#define NR_LOCKS 16
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/*
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* Ensure each lock is in a separate cacheline.
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*/
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static union {
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raw_spinlock_t lock;
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char pad[L1_CACHE_BYTES];
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} atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp = {
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[0 ... (NR_LOCKS - 1)] = {
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.lock = __RAW_SPIN_LOCK_UNLOCKED(atomic64_lock.lock),
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},
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};
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static inline raw_spinlock_t *lock_addr(const atomic64_t *v)
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{
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unsigned long addr = (unsigned long) v;
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addr >>= L1_CACHE_SHIFT;
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addr ^= (addr >> 8) ^ (addr >> 16);
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return &atomic64_lock[addr & (NR_LOCKS - 1)].lock;
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}
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s64 generic_atomic64_read(const atomic64_t *v)
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{
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unsigned long flags;
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raw_spinlock_t *lock = lock_addr(v);
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s64 val;
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raw_spin_lock_irqsave(lock, flags);
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val = v->counter;
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raw_spin_unlock_irqrestore(lock, flags);
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return val;
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}
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EXPORT_SYMBOL(generic_atomic64_read);
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void generic_atomic64_set(atomic64_t *v, s64 i)
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{
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unsigned long flags;
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raw_spinlock_t *lock = lock_addr(v);
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raw_spin_lock_irqsave(lock, flags);
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v->counter = i;
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raw_spin_unlock_irqrestore(lock, flags);
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}
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EXPORT_SYMBOL(generic_atomic64_set);
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#define ATOMIC64_OP(op, c_op) \
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void generic_atomic64_##op(s64 a, atomic64_t *v) \
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{ \
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unsigned long flags; \
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raw_spinlock_t *lock = lock_addr(v); \
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\
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raw_spin_lock_irqsave(lock, flags); \
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v->counter c_op a; \
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raw_spin_unlock_irqrestore(lock, flags); \
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} \
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EXPORT_SYMBOL(generic_atomic64_##op);
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#define ATOMIC64_OP_RETURN(op, c_op) \
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s64 generic_atomic64_##op##_return(s64 a, atomic64_t *v) \
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{ \
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unsigned long flags; \
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raw_spinlock_t *lock = lock_addr(v); \
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s64 val; \
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\
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raw_spin_lock_irqsave(lock, flags); \
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val = (v->counter c_op a); \
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raw_spin_unlock_irqrestore(lock, flags); \
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return val; \
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} \
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EXPORT_SYMBOL(generic_atomic64_##op##_return);
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#define ATOMIC64_FETCH_OP(op, c_op) \
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s64 generic_atomic64_fetch_##op(s64 a, atomic64_t *v) \
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{ \
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unsigned long flags; \
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raw_spinlock_t *lock = lock_addr(v); \
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s64 val; \
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\
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raw_spin_lock_irqsave(lock, flags); \
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val = v->counter; \
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v->counter c_op a; \
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raw_spin_unlock_irqrestore(lock, flags); \
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return val; \
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} \
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EXPORT_SYMBOL(generic_atomic64_fetch_##op);
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#define ATOMIC64_OPS(op, c_op) \
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ATOMIC64_OP(op, c_op) \
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ATOMIC64_OP_RETURN(op, c_op) \
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ATOMIC64_FETCH_OP(op, c_op)
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ATOMIC64_OPS(add, +=)
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ATOMIC64_OPS(sub, -=)
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, c_op) \
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ATOMIC64_OP(op, c_op) \
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ATOMIC64_FETCH_OP(op, c_op)
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ATOMIC64_OPS(and, &=)
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ATOMIC64_OPS(or, |=)
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ATOMIC64_OPS(xor, ^=)
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP
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s64 generic_atomic64_dec_if_positive(atomic64_t *v)
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{
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unsigned long flags;
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raw_spinlock_t *lock = lock_addr(v);
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s64 val;
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raw_spin_lock_irqsave(lock, flags);
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val = v->counter - 1;
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if (val >= 0)
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v->counter = val;
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raw_spin_unlock_irqrestore(lock, flags);
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return val;
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}
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EXPORT_SYMBOL(generic_atomic64_dec_if_positive);
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s64 generic_atomic64_cmpxchg(atomic64_t *v, s64 o, s64 n)
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{
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unsigned long flags;
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raw_spinlock_t *lock = lock_addr(v);
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s64 val;
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raw_spin_lock_irqsave(lock, flags);
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val = v->counter;
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if (val == o)
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v->counter = n;
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raw_spin_unlock_irqrestore(lock, flags);
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return val;
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}
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EXPORT_SYMBOL(generic_atomic64_cmpxchg);
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s64 generic_atomic64_xchg(atomic64_t *v, s64 new)
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{
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unsigned long flags;
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raw_spinlock_t *lock = lock_addr(v);
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s64 val;
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raw_spin_lock_irqsave(lock, flags);
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val = v->counter;
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v->counter = new;
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raw_spin_unlock_irqrestore(lock, flags);
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return val;
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}
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EXPORT_SYMBOL(generic_atomic64_xchg);
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s64 generic_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
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{
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unsigned long flags;
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raw_spinlock_t *lock = lock_addr(v);
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s64 val;
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raw_spin_lock_irqsave(lock, flags);
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val = v->counter;
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if (val != u)
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v->counter += a;
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raw_spin_unlock_irqrestore(lock, flags);
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return val;
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}
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EXPORT_SYMBOL(generic_atomic64_fetch_add_unless);
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