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e11a47f520
The PXA168 has a peculiar setup with the AXI clock enable control for the SDHC controllers. The bits in the SDH0 register control the AXI clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2 register control both SDH2 and SDH3. This is modeled with two new parentless clocks that control the shared bits. Previously, SDH0 had to be enabled in order for SDH1 to be used, and when SDH1 was enabled, unused bits in the SDH1 register were being controlled. This fixes those issues. A future commit will add support for these new shared clocks to be enabled by the PXA168 SDHC driver. Signed-off-by: Doug Brown <doug@schmorgal.com> Link: https://lore.kernel.org/r/20220612192937.162952-13-doug@schmorgal.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| .. | ||
| clk-apbc.c | ||
| clk-apmu.c | ||
| clk-audio.c | ||
| clk-frac.c | ||
| clk-gate.c | ||
| clk-mix.c | ||
| clk-mmp2.c | ||
| clk-of-mmp2.c | ||
| clk-of-pxa168.c | ||
| clk-of-pxa910.c | ||
| clk-of-pxa1928.c | ||
| clk-pll.c | ||
| clk-pxa168.c | ||
| clk-pxa910.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| pwr-island.c | ||
| reset.c | ||
| reset.h | ||