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cd795fb0c3
Add CMDQ driver support for mt8188 by adding its compatible and driver data in CMDQ driver. Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
793 lines
20 KiB
C
793 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2018 MediaTek Inc.
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/mailbox_controller.h>
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#include <linux/mailbox/mtk-cmdq-mailbox.h>
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#include <linux/of.h>
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#define CMDQ_MBOX_AUTOSUSPEND_DELAY_MS 100
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#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
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#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
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#define CMDQ_GCE_NUM_MAX (2)
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#define CMDQ_CURR_IRQ_STATUS 0x10
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#define CMDQ_SYNC_TOKEN_UPDATE 0x68
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#define CMDQ_THR_SLOT_CYCLES 0x30
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#define CMDQ_THR_BASE 0x100
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#define CMDQ_THR_SIZE 0x80
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#define CMDQ_THR_WARM_RESET 0x00
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#define CMDQ_THR_ENABLE_TASK 0x04
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#define CMDQ_THR_SUSPEND_TASK 0x08
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#define CMDQ_THR_CURR_STATUS 0x0c
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#define CMDQ_THR_IRQ_STATUS 0x10
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#define CMDQ_THR_IRQ_ENABLE 0x14
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#define CMDQ_THR_CURR_ADDR 0x20
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#define CMDQ_THR_END_ADDR 0x24
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#define CMDQ_THR_WAIT_TOKEN 0x30
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#define CMDQ_THR_PRIORITY 0x40
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#define GCE_GCTL_VALUE 0x48
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#define GCE_CTRL_BY_SW GENMASK(2, 0)
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#define GCE_DDR_EN GENMASK(18, 16)
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#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
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#define CMDQ_THR_ENABLED 0x1
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#define CMDQ_THR_DISABLED 0x0
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#define CMDQ_THR_SUSPEND 0x1
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#define CMDQ_THR_RESUME 0x0
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#define CMDQ_THR_STATUS_SUSPENDED BIT(1)
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#define CMDQ_THR_DO_WARM_RESET BIT(0)
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#define CMDQ_THR_IRQ_DONE 0x1
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#define CMDQ_THR_IRQ_ERROR 0x12
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#define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
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#define CMDQ_THR_IS_WAITING BIT(31)
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#define CMDQ_JUMP_BY_OFFSET 0x10000000
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#define CMDQ_JUMP_BY_PA 0x10000001
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struct cmdq_thread {
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struct mbox_chan *chan;
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void __iomem *base;
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struct list_head task_busy_list;
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u32 priority;
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};
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struct cmdq_task {
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struct cmdq *cmdq;
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struct list_head list_entry;
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dma_addr_t pa_base;
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struct cmdq_thread *thread;
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struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
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};
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struct cmdq {
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struct mbox_controller mbox;
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void __iomem *base;
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int irq;
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u32 irq_mask;
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const struct gce_plat *pdata;
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struct cmdq_thread *thread;
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struct clk_bulk_data clocks[CMDQ_GCE_NUM_MAX];
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bool suspended;
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};
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struct gce_plat {
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u32 thread_nr;
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u8 shift;
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bool control_by_sw;
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bool sw_ddr_en;
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u32 gce_num;
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};
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static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
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{
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WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
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if (enable)
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writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
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else
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writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
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clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
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}
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u8 cmdq_get_shift_pa(struct mbox_chan *chan)
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{
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struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
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return cmdq->pdata->shift;
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}
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EXPORT_SYMBOL(cmdq_get_shift_pa);
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static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
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{
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u32 status;
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writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
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/* If already disabled, treat as suspended successful. */
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if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
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return 0;
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if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
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status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
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dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
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(u32)(thread->base - cmdq->base));
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return -EFAULT;
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}
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return 0;
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}
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static void cmdq_thread_resume(struct cmdq_thread *thread)
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{
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writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
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}
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static void cmdq_init(struct cmdq *cmdq)
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{
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int i;
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u32 gctl_regval = 0;
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WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
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if (cmdq->pdata->control_by_sw)
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gctl_regval = GCE_CTRL_BY_SW;
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if (cmdq->pdata->sw_ddr_en)
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gctl_regval |= GCE_DDR_EN;
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if (gctl_regval)
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writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE);
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writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
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for (i = 0; i <= CMDQ_MAX_EVENT; i++)
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writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
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clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
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}
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static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
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{
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u32 warm_reset;
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writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
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if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
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warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
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0, 10)) {
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dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
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(u32)(thread->base - cmdq->base));
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return -EFAULT;
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}
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return 0;
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}
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static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
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{
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cmdq_thread_reset(cmdq, thread);
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writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
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}
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/* notify GCE to re-fetch commands by setting GCE thread PC */
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static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
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{
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writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
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thread->base + CMDQ_THR_CURR_ADDR);
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}
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static void cmdq_task_insert_into_thread(struct cmdq_task *task)
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{
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struct device *dev = task->cmdq->mbox.dev;
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struct cmdq_thread *thread = task->thread;
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struct cmdq_task *prev_task = list_last_entry(
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&thread->task_busy_list, typeof(*task), list_entry);
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u64 *prev_task_base = prev_task->pkt->va_base;
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/* let previous task jump to this task */
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dma_sync_single_for_cpu(dev, prev_task->pa_base,
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prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
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prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
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(u64)CMDQ_JUMP_BY_PA << 32 |
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(task->pa_base >> task->cmdq->pdata->shift);
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dma_sync_single_for_device(dev, prev_task->pa_base,
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prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
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cmdq_thread_invalidate_fetched_data(thread);
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}
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static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
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{
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return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
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}
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static void cmdq_task_exec_done(struct cmdq_task *task, int sta)
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{
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struct cmdq_cb_data data;
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data.sta = sta;
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data.pkt = task->pkt;
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mbox_chan_received_data(task->thread->chan, &data);
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list_del(&task->list_entry);
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}
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static void cmdq_task_handle_error(struct cmdq_task *task)
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{
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struct cmdq_thread *thread = task->thread;
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struct cmdq_task *next_task;
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struct cmdq *cmdq = task->cmdq;
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dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
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WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
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next_task = list_first_entry_or_null(&thread->task_busy_list,
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struct cmdq_task, list_entry);
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if (next_task)
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writel(next_task->pa_base >> cmdq->pdata->shift,
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thread->base + CMDQ_THR_CURR_ADDR);
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cmdq_thread_resume(thread);
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}
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static void cmdq_thread_irq_handler(struct cmdq *cmdq,
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struct cmdq_thread *thread)
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{
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struct cmdq_task *task, *tmp, *curr_task = NULL;
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u32 curr_pa, irq_flag, task_end_pa;
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bool err;
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irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
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writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
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/*
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* When ISR call this function, another CPU core could run
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* "release task" right before we acquire the spin lock, and thus
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* reset / disable this GCE thread, so we need to check the enable
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* bit of this GCE thread.
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*/
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if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
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return;
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if (irq_flag & CMDQ_THR_IRQ_ERROR)
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err = true;
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else if (irq_flag & CMDQ_THR_IRQ_DONE)
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err = false;
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else
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return;
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curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->pdata->shift;
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list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
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list_entry) {
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task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
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if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
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curr_task = task;
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if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
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cmdq_task_exec_done(task, 0);
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kfree(task);
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} else if (err) {
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cmdq_task_exec_done(task, -ENOEXEC);
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cmdq_task_handle_error(curr_task);
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kfree(task);
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}
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if (curr_task)
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break;
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}
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if (list_empty(&thread->task_busy_list))
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cmdq_thread_disable(cmdq, thread);
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}
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static irqreturn_t cmdq_irq_handler(int irq, void *dev)
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{
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struct cmdq *cmdq = dev;
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unsigned long irq_status, flags = 0L;
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int bit;
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irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
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if (!(irq_status ^ cmdq->irq_mask))
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return IRQ_NONE;
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for_each_clear_bit(bit, &irq_status, cmdq->pdata->thread_nr) {
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struct cmdq_thread *thread = &cmdq->thread[bit];
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spin_lock_irqsave(&thread->chan->lock, flags);
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cmdq_thread_irq_handler(cmdq, thread);
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spin_unlock_irqrestore(&thread->chan->lock, flags);
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}
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pm_runtime_mark_last_busy(cmdq->mbox.dev);
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return IRQ_HANDLED;
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}
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static int cmdq_runtime_resume(struct device *dev)
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{
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struct cmdq *cmdq = dev_get_drvdata(dev);
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return clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks);
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}
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static int cmdq_runtime_suspend(struct device *dev)
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{
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struct cmdq *cmdq = dev_get_drvdata(dev);
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clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
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return 0;
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}
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static int cmdq_suspend(struct device *dev)
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{
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struct cmdq *cmdq = dev_get_drvdata(dev);
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struct cmdq_thread *thread;
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int i;
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bool task_running = false;
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cmdq->suspended = true;
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for (i = 0; i < cmdq->pdata->thread_nr; i++) {
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thread = &cmdq->thread[i];
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if (!list_empty(&thread->task_busy_list)) {
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task_running = true;
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break;
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}
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}
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if (task_running)
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dev_warn(dev, "exist running task(s) in suspend\n");
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if (cmdq->pdata->sw_ddr_en)
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cmdq_sw_ddr_enable(cmdq, false);
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return pm_runtime_force_suspend(dev);
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}
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static int cmdq_resume(struct device *dev)
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{
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struct cmdq *cmdq = dev_get_drvdata(dev);
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WARN_ON(pm_runtime_force_resume(dev));
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cmdq->suspended = false;
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if (cmdq->pdata->sw_ddr_en)
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cmdq_sw_ddr_enable(cmdq, true);
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return 0;
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}
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static void cmdq_remove(struct platform_device *pdev)
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{
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struct cmdq *cmdq = platform_get_drvdata(pdev);
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if (cmdq->pdata->sw_ddr_en)
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cmdq_sw_ddr_enable(cmdq, false);
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if (!IS_ENABLED(CONFIG_PM))
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cmdq_runtime_suspend(&pdev->dev);
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clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks);
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}
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static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
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{
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struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
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struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
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struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
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struct cmdq_task *task;
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unsigned long curr_pa, end_pa;
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int ret;
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/* Client should not flush new tasks if suspended. */
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WARN_ON(cmdq->suspended);
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ret = pm_runtime_get_sync(cmdq->mbox.dev);
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if (ret < 0)
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return ret;
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task = kzalloc(sizeof(*task), GFP_ATOMIC);
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if (!task) {
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pm_runtime_put_autosuspend(cmdq->mbox.dev);
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return -ENOMEM;
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}
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task->cmdq = cmdq;
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INIT_LIST_HEAD(&task->list_entry);
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task->pa_base = pkt->pa_base;
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task->thread = thread;
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task->pkt = pkt;
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if (list_empty(&thread->task_busy_list)) {
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/*
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* The thread reset will clear thread related register to 0,
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* including pc, end, priority, irq, suspend and enable. Thus
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* set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
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* thread and make it running.
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*/
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WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
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writel(task->pa_base >> cmdq->pdata->shift,
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thread->base + CMDQ_THR_CURR_ADDR);
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writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
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thread->base + CMDQ_THR_END_ADDR);
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writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
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writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
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writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
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} else {
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WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
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curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
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cmdq->pdata->shift;
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end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
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cmdq->pdata->shift;
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/* check boundary */
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if (curr_pa == end_pa - CMDQ_INST_SIZE ||
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curr_pa == end_pa) {
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/* set to this task directly */
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writel(task->pa_base >> cmdq->pdata->shift,
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thread->base + CMDQ_THR_CURR_ADDR);
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} else {
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cmdq_task_insert_into_thread(task);
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smp_mb(); /* modify jump before enable thread */
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}
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writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
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thread->base + CMDQ_THR_END_ADDR);
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cmdq_thread_resume(thread);
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}
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list_move_tail(&task->list_entry, &thread->task_busy_list);
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pm_runtime_mark_last_busy(cmdq->mbox.dev);
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pm_runtime_put_autosuspend(cmdq->mbox.dev);
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return 0;
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}
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static int cmdq_mbox_startup(struct mbox_chan *chan)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void cmdq_mbox_shutdown(struct mbox_chan *chan)
|
|
{
|
|
struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
|
|
struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
|
|
struct cmdq_task *task, *tmp;
|
|
unsigned long flags;
|
|
|
|
WARN_ON(pm_runtime_get_sync(cmdq->mbox.dev));
|
|
|
|
spin_lock_irqsave(&thread->chan->lock, flags);
|
|
if (list_empty(&thread->task_busy_list))
|
|
goto done;
|
|
|
|
WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
|
|
|
|
/* make sure executed tasks have success callback */
|
|
cmdq_thread_irq_handler(cmdq, thread);
|
|
if (list_empty(&thread->task_busy_list))
|
|
goto done;
|
|
|
|
list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
|
|
list_entry) {
|
|
cmdq_task_exec_done(task, -ECONNABORTED);
|
|
kfree(task);
|
|
}
|
|
|
|
cmdq_thread_disable(cmdq, thread);
|
|
|
|
done:
|
|
/*
|
|
* The thread->task_busy_list empty means thread already disable. The
|
|
* cmdq_mbox_send_data() always reset thread which clear disable and
|
|
* suspend statue when first pkt send to channel, so there is no need
|
|
* to do any operation here, only unlock and leave.
|
|
*/
|
|
spin_unlock_irqrestore(&thread->chan->lock, flags);
|
|
|
|
pm_runtime_mark_last_busy(cmdq->mbox.dev);
|
|
pm_runtime_put_autosuspend(cmdq->mbox.dev);
|
|
}
|
|
|
|
static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
|
|
{
|
|
struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
|
|
struct cmdq_cb_data data;
|
|
struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
|
|
struct cmdq_task *task, *tmp;
|
|
unsigned long flags;
|
|
u32 enable;
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(cmdq->mbox.dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
spin_lock_irqsave(&thread->chan->lock, flags);
|
|
if (list_empty(&thread->task_busy_list))
|
|
goto out;
|
|
|
|
WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
|
|
if (!cmdq_thread_is_in_wfe(thread))
|
|
goto wait;
|
|
|
|
list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
|
|
list_entry) {
|
|
data.sta = -ECONNABORTED;
|
|
data.pkt = task->pkt;
|
|
mbox_chan_received_data(task->thread->chan, &data);
|
|
list_del(&task->list_entry);
|
|
kfree(task);
|
|
}
|
|
|
|
cmdq_thread_resume(thread);
|
|
cmdq_thread_disable(cmdq, thread);
|
|
|
|
out:
|
|
spin_unlock_irqrestore(&thread->chan->lock, flags);
|
|
pm_runtime_mark_last_busy(cmdq->mbox.dev);
|
|
pm_runtime_put_autosuspend(cmdq->mbox.dev);
|
|
|
|
return 0;
|
|
|
|
wait:
|
|
cmdq_thread_resume(thread);
|
|
spin_unlock_irqrestore(&thread->chan->lock, flags);
|
|
if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK,
|
|
enable, enable == 0, 1, timeout)) {
|
|
dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n",
|
|
(u32)(thread->base - cmdq->base));
|
|
|
|
return -EFAULT;
|
|
}
|
|
pm_runtime_mark_last_busy(cmdq->mbox.dev);
|
|
pm_runtime_put_autosuspend(cmdq->mbox.dev);
|
|
return 0;
|
|
}
|
|
|
|
static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
|
|
.send_data = cmdq_mbox_send_data,
|
|
.startup = cmdq_mbox_startup,
|
|
.shutdown = cmdq_mbox_shutdown,
|
|
.flush = cmdq_mbox_flush,
|
|
};
|
|
|
|
static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
|
|
const struct of_phandle_args *sp)
|
|
{
|
|
int ind = sp->args[0];
|
|
struct cmdq_thread *thread;
|
|
|
|
if (ind >= mbox->num_chans)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
|
|
thread->priority = sp->args[1];
|
|
thread->chan = &mbox->chans[ind];
|
|
|
|
return &mbox->chans[ind];
|
|
}
|
|
|
|
static int cmdq_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct cmdq *cmdq;
|
|
int err, i;
|
|
struct device_node *phandle = dev->of_node;
|
|
struct device_node *node;
|
|
int alias_id = 0;
|
|
static const char * const clk_name = "gce";
|
|
static const char * const clk_names[] = { "gce0", "gce1" };
|
|
|
|
cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
|
|
if (!cmdq)
|
|
return -ENOMEM;
|
|
|
|
cmdq->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(cmdq->base))
|
|
return PTR_ERR(cmdq->base);
|
|
|
|
cmdq->irq = platform_get_irq(pdev, 0);
|
|
if (cmdq->irq < 0)
|
|
return cmdq->irq;
|
|
|
|
cmdq->pdata = device_get_match_data(dev);
|
|
if (!cmdq->pdata) {
|
|
dev_err(dev, "failed to get match data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
cmdq->irq_mask = GENMASK(cmdq->pdata->thread_nr - 1, 0);
|
|
|
|
dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
|
|
dev, cmdq->base, cmdq->irq);
|
|
|
|
if (cmdq->pdata->gce_num > 1) {
|
|
for_each_child_of_node(phandle->parent, node) {
|
|
alias_id = of_alias_get_id(node, clk_name);
|
|
if (alias_id >= 0 && alias_id < cmdq->pdata->gce_num) {
|
|
cmdq->clocks[alias_id].id = clk_names[alias_id];
|
|
cmdq->clocks[alias_id].clk = of_clk_get(node, 0);
|
|
if (IS_ERR(cmdq->clocks[alias_id].clk)) {
|
|
of_node_put(node);
|
|
return dev_err_probe(dev,
|
|
PTR_ERR(cmdq->clocks[alias_id].clk),
|
|
"failed to get gce clk: %d\n",
|
|
alias_id);
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
cmdq->clocks[alias_id].id = clk_name;
|
|
cmdq->clocks[alias_id].clk = devm_clk_get(&pdev->dev, clk_name);
|
|
if (IS_ERR(cmdq->clocks[alias_id].clk)) {
|
|
return dev_err_probe(dev, PTR_ERR(cmdq->clocks[alias_id].clk),
|
|
"failed to get gce clk\n");
|
|
}
|
|
}
|
|
|
|
cmdq->mbox.dev = dev;
|
|
cmdq->mbox.chans = devm_kcalloc(dev, cmdq->pdata->thread_nr,
|
|
sizeof(*cmdq->mbox.chans), GFP_KERNEL);
|
|
if (!cmdq->mbox.chans)
|
|
return -ENOMEM;
|
|
|
|
cmdq->mbox.num_chans = cmdq->pdata->thread_nr;
|
|
cmdq->mbox.ops = &cmdq_mbox_chan_ops;
|
|
cmdq->mbox.of_xlate = cmdq_xlate;
|
|
|
|
/* make use of TXDONE_BY_ACK */
|
|
cmdq->mbox.txdone_irq = false;
|
|
cmdq->mbox.txdone_poll = false;
|
|
|
|
cmdq->thread = devm_kcalloc(dev, cmdq->pdata->thread_nr,
|
|
sizeof(*cmdq->thread), GFP_KERNEL);
|
|
if (!cmdq->thread)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < cmdq->pdata->thread_nr; i++) {
|
|
cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
|
|
CMDQ_THR_SIZE * i;
|
|
INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
|
|
cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
|
|
}
|
|
|
|
err = devm_mbox_controller_register(dev, &cmdq->mbox);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to register mailbox: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, cmdq);
|
|
|
|
WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks));
|
|
|
|
cmdq_init(cmdq);
|
|
|
|
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
|
|
"mtk_cmdq", cmdq);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to register ISR (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
/* If Runtime PM is not available enable the clocks now. */
|
|
if (!IS_ENABLED(CONFIG_PM)) {
|
|
err = cmdq_runtime_resume(dev);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
err = devm_pm_runtime_enable(dev);
|
|
if (err)
|
|
return err;
|
|
|
|
pm_runtime_set_autosuspend_delay(dev, CMDQ_MBOX_AUTOSUSPEND_DELAY_MS);
|
|
pm_runtime_use_autosuspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops cmdq_pm_ops = {
|
|
.suspend = cmdq_suspend,
|
|
.resume = cmdq_resume,
|
|
SET_RUNTIME_PM_OPS(cmdq_runtime_suspend,
|
|
cmdq_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct gce_plat gce_plat_mt6779 = {
|
|
.thread_nr = 24,
|
|
.shift = 3,
|
|
.control_by_sw = false,
|
|
.gce_num = 1
|
|
};
|
|
|
|
static const struct gce_plat gce_plat_mt8173 = {
|
|
.thread_nr = 16,
|
|
.shift = 0,
|
|
.control_by_sw = false,
|
|
.gce_num = 1
|
|
};
|
|
|
|
static const struct gce_plat gce_plat_mt8183 = {
|
|
.thread_nr = 24,
|
|
.shift = 0,
|
|
.control_by_sw = false,
|
|
.gce_num = 1
|
|
};
|
|
|
|
static const struct gce_plat gce_plat_mt8186 = {
|
|
.thread_nr = 24,
|
|
.shift = 3,
|
|
.control_by_sw = true,
|
|
.sw_ddr_en = true,
|
|
.gce_num = 1
|
|
};
|
|
|
|
static const struct gce_plat gce_plat_mt8188 = {
|
|
.thread_nr = 32,
|
|
.shift = 3,
|
|
.control_by_sw = true,
|
|
.gce_num = 2
|
|
};
|
|
|
|
static const struct gce_plat gce_plat_mt8192 = {
|
|
.thread_nr = 24,
|
|
.shift = 3,
|
|
.control_by_sw = true,
|
|
.gce_num = 1
|
|
};
|
|
|
|
static const struct gce_plat gce_plat_mt8195 = {
|
|
.thread_nr = 24,
|
|
.shift = 3,
|
|
.control_by_sw = true,
|
|
.gce_num = 2
|
|
};
|
|
|
|
static const struct of_device_id cmdq_of_ids[] = {
|
|
{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_mt6779},
|
|
{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_mt8173},
|
|
{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_mt8183},
|
|
{.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_mt8186},
|
|
{.compatible = "mediatek,mt8188-gce", .data = (void *)&gce_plat_mt8188},
|
|
{.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_mt8192},
|
|
{.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_mt8195},
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver cmdq_drv = {
|
|
.probe = cmdq_probe,
|
|
.remove_new = cmdq_remove,
|
|
.driver = {
|
|
.name = "mtk_cmdq",
|
|
.pm = &cmdq_pm_ops,
|
|
.of_match_table = cmdq_of_ids,
|
|
}
|
|
};
|
|
|
|
static int __init cmdq_drv_init(void)
|
|
{
|
|
return platform_driver_register(&cmdq_drv);
|
|
}
|
|
|
|
static void __exit cmdq_drv_exit(void)
|
|
{
|
|
platform_driver_unregister(&cmdq_drv);
|
|
}
|
|
|
|
subsys_initcall(cmdq_drv_init);
|
|
module_exit(cmdq_drv_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|