Palmer Dabbelt 61a9b71290 Merge patch series "Putting some basic order on isa extension lists" ... This cleans up the ISA string handling to more closely match a version of the ISA spec. This is visible in /proc/cpuinfo and the ordering changes may break something in userspace, but these orderings have changed before without issues so with any luck that's still the case. This also adds documentation so userspace has a better idea of what is intended when it comes to compatibility for /proc/cpuinfo, which should help everyone as this will likely keep changing. * b4-shazam-merge: Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo RISC-V: resort all extensions in consistent orders RISC-V: clarify ISA string ordering rules in cpu.c Link: https://lore.kernel.org/r/20221205144525.2148448-1-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-01-19 16:41:04 -08:00
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boot-image-header.rst	RISC-V: Typo fixes in image header and documentation.	2019-12-19 09:32:45 -07:00
features.rst	docs: archis: add a per-architecture features list	2020-12-03 15:10:15 -07:00
index.rst	doc: RISC-V: Document that misaligned accesses are supported	2022-10-12 08:58:10 -07:00
patch-acceptance.rst	Documentation: RISC-V: patch-acceptance: s/implementor/implementer	2022-12-13 09:38:28 -08:00
uabi.rst	Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo	2023-01-17 22:05:33 -08:00
vm-layout.rst	Documentation: riscv: Document the sv57 VM layout	2022-11-21 14:40:26 -07:00