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60bed79840
Remove 0x prefix from clkctrl unit address. This silences the following dtc warning: Warning (unit_address_format): Node /clkctrl@0xf8000000 unit name should not have leading "0x" Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
244 lines
7.0 KiB
Plaintext
244 lines
7.0 KiB
Plaintext
/*
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* Device Tree Source for the Axis ARTPEC-6 SoC
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "axis,artpec6";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&pl310>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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next-level-cache = <&pl310>;
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};
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};
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syscon: syscon@f8000000 {
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compatible = "axis,artpec6-syscon", "syscon";
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reg = <0xf8000000 0x48>;
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};
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psci {
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compatible = "arm,psci-0.2", "arm,psci";
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method = "smc";
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psci_version = <0x84000000>;
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cpu_on = <0x84000003>;
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system_reset = <0x84000009>;
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};
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scu@faf00000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xfaf00000 0x58>;
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};
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/* Main external clock driving CPU and peripherals */
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ext_clk: ext_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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eth_phy_ref_clk: eth_phy_ref_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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};
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clkctrl: clkctrl@f8000000 {
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#clock-cells = <1>;
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compatible = "axis,artpec6-clkctrl";
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reg = <0xf8000000 0x48>;
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clocks = <&ext_clk>;
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clock-names = "sys_refclk";
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};
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gtimer@faf00200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xfaf00200 0x20>;
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interrupts = <GIC_PPI 11 0xf01>;
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clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
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};
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timer@faf00600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfaf00600 0x20>;
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interrupts = <GIC_PPI 13 0xf04>;
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clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
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status = "disabled";
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};
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intc: interrupt-controller@faf01000 {
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interrupt-controller;
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
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};
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pl310: cache-controller@faf10000 {
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compatible = "arm,pl310-cache";
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cache-unified;
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cache-level = <2>;
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reg = <0xfaf10000 0x1000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <1 1 1>;
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arm,filter-ranges = <0x0 0x80000000>;
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arm,double-linefill = <1>;
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arm,double-linefill-incr = <0>;
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arm,double-linefill-wrap = <0>;
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prefetch-data = <1>;
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prefetch-instr = <1>;
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arm,prefetch-offset = <0>;
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arm,prefetch-drop = <1>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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pcie: pcie@f8050000 {
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compatible = "axis,artpec6-pcie", "snps,dw-pcie";
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reg = <0xf8050000 0x2000
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0xf8040000 0x1000
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0xc0000000 0x2000>;
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reg-names = "dbi", "phy", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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/* downstream I/O */
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ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
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/* non-prefetchable memory */
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0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
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num-lanes = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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axis,syscon-pcie = <&syscon>;
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status = "disabled";
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};
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amba@0 {
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compatible = "simple-bus";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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dma-ranges;
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ethernet: ethernet@f8010000 {
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clock-names = "phy_ref_clk", "apb_pclk";
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clocks = <ð_phy_ref_clk>,
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<&clkctrl ARTPEC6_CLK_ETH_ACLK>;
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compatible = "snps,dwc-qos-ethernet-4.10";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf8010000 0x4000>;
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snps,write-requests = <2>;
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snps,read-requests = <16>;
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snps,txpbl = <8>;
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snps,rxpbl = <2>;
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status = "disabled";
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};
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uart0: serial@f8036000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8036000 0x1000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
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<&clkctrl ARTPEC6_CLK_UART_PCLK>;
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clock-names = "uart_clk", "apb_pclk";
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status = "disabled";
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};
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uart1: serial@f8037000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8037000 0x1000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
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<&clkctrl ARTPEC6_CLK_UART_PCLK>;
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clock-names = "uart_clk", "apb_pclk";
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status = "disabled";
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};
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uart2: serial@f8038000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8038000 0x1000>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
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<&clkctrl ARTPEC6_CLK_UART_PCLK>;
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clock-names = "uart_clk", "apb_pclk";
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status = "disabled";
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};
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uart3: serial@f8039000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8039000 0x1000>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
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<&clkctrl ARTPEC6_CLK_UART_PCLK>;
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clock-names = "uart_clk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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