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Tegra PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 through Tegra210 and currently Tegra clock driver keeps the audio mclk enabled. With the move of PMC clocks from clock driver into pmc driver, audio mclk enable from clock driver is removed and this should be taken care of by the audio driver. tegra_asoc_utils_init() calls tegra_asoc_utils_set_rate() and audio mclk rate configuration is not needed during init and the rate is actually set during the ->hw_params() callback. So, this patch removes tegra_asoc_utils_set_rate() call and just leaves the audio mclk enabled. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
226 lines
5.5 KiB
C
226 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* tegra_asoc_utils.c - Harmony machine ASoC driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010,2012 - NVIDIA, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include "tegra_asoc_utils.h"
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int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
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int mclk)
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{
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int new_baseclock;
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bool clk_change;
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int err;
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switch (srate) {
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case 11025:
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case 22050:
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case 44100:
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case 88200:
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if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
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new_baseclock = 56448000;
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else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
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new_baseclock = 564480000;
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else
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new_baseclock = 282240000;
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break;
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case 8000:
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case 16000:
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case 32000:
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case 48000:
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case 64000:
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case 96000:
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if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
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new_baseclock = 73728000;
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else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
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new_baseclock = 552960000;
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else
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new_baseclock = 368640000;
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break;
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default:
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return -EINVAL;
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}
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clk_change = ((new_baseclock != data->set_baseclock) ||
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(mclk != data->set_mclk));
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if (!clk_change)
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return 0;
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data->set_baseclock = 0;
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data->set_mclk = 0;
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clk_disable_unprepare(data->clk_cdev1);
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err = clk_set_rate(data->clk_pll_a, new_baseclock);
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if (err) {
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dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
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return err;
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}
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err = clk_set_rate(data->clk_pll_a_out0, mclk);
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if (err) {
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dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
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return err;
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}
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/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
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err = clk_prepare_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", err);
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return err;
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}
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data->set_baseclock = new_baseclock;
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data->set_mclk = mclk;
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
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int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
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{
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const int pll_rate = 73728000;
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const int ac97_rate = 24576000;
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int err;
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clk_disable_unprepare(data->clk_cdev1);
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/*
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* AC97 rate is fixed at 24.576MHz and is used for both the host
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* controller and the external codec
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*/
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err = clk_set_rate(data->clk_pll_a, pll_rate);
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if (err) {
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dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
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return err;
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}
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err = clk_set_rate(data->clk_pll_a_out0, ac97_rate);
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if (err) {
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dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
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return err;
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}
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/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
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err = clk_prepare_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", err);
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return err;
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}
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data->set_baseclock = pll_rate;
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data->set_mclk = ac97_rate;
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate);
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int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
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struct device *dev)
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{
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struct clk *clk_out_1, *clk_extern1;
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int ret;
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data->dev = dev;
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if (of_machine_is_compatible("nvidia,tegra20"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
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else if (of_machine_is_compatible("nvidia,tegra30"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30;
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else if (of_machine_is_compatible("nvidia,tegra114"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA114;
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else if (of_machine_is_compatible("nvidia,tegra124"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA124;
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else {
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dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n");
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return -EINVAL;
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}
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data->clk_pll_a = devm_clk_get(dev, "pll_a");
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if (IS_ERR(data->clk_pll_a)) {
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dev_err(data->dev, "Can't retrieve clk pll_a\n");
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return PTR_ERR(data->clk_pll_a);
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}
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data->clk_pll_a_out0 = devm_clk_get(dev, "pll_a_out0");
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if (IS_ERR(data->clk_pll_a_out0)) {
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dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
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return PTR_ERR(data->clk_pll_a_out0);
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}
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data->clk_cdev1 = devm_clk_get(dev, "mclk");
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if (IS_ERR(data->clk_cdev1)) {
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dev_err(data->dev, "Can't retrieve clk cdev1\n");
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return PTR_ERR(data->clk_cdev1);
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}
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/*
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* If clock parents are not set in DT, configure here to use clk_out_1
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* as mclk and extern1 as parent for Tegra30 and higher.
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*/
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if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
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data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) {
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dev_warn(data->dev,
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"Configuring clocks for a legacy device-tree\n");
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dev_warn(data->dev,
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"Please update DT to use assigned-clock-parents\n");
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clk_extern1 = devm_clk_get(dev, "extern1");
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if (IS_ERR(clk_extern1)) {
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dev_err(data->dev, "Can't retrieve clk extern1\n");
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return PTR_ERR(clk_extern1);
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}
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ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0);
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if (ret < 0) {
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dev_err(data->dev,
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"Set parent failed for clk extern1\n");
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return ret;
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}
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clk_out_1 = devm_clk_get(dev, "pmc_clk_out_1");
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if (IS_ERR(clk_out_1)) {
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dev_err(data->dev, "Can't retrieve pmc_clk_out_1\n");
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return PTR_ERR(clk_out_1);
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}
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ret = clk_set_parent(clk_out_1, clk_extern1);
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if (ret < 0) {
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dev_err(data->dev,
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"Set parent failed for pmc_clk_out_1\n");
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return ret;
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}
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data->clk_cdev1 = clk_out_1;
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}
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/*
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* FIXME: There is some unknown dependency between audio mclk disable
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* and suspend-resume functionality on Tegra30, although audio mclk is
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* only needed for audio.
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*/
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ret = clk_prepare_enable(data->clk_cdev1);
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if (ret) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", ret);
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
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MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
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MODULE_DESCRIPTION("Tegra ASoC utility code");
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MODULE_LICENSE("GPL");
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