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7251b9e8a0
CPU temperature can be negative in some cases. Thus the negative CPU
temperature should not be considered as a failure.
Fix intel_tcc_get_temp() and its users to support negative CPU
temperature.
Fixes: a3c1f066e1 ("thermal/intel: Introduce Intel TCC library")
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Cc: 6.3+ <stable@vger.kernel.org> # 6.3+
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access
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* Copyright (c) 2022, Intel Corporation.
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*/
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#include <linux/errno.h>
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#include <linux/intel_tcc.h>
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#include <asm/msr.h>
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/**
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* intel_tcc_get_tjmax() - returns the default TCC activation Temperature
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* @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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*
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* Get the TjMax value, which is the default thermal throttling or TCC
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* activation temperature in degrees C.
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*
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* Return: Tjmax value in degrees C on success, negative error code otherwise.
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*/
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int intel_tcc_get_tjmax(int cpu)
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{
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u32 low, high;
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int val, err;
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if (cpu < 0)
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err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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else
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err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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if (err)
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return err;
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val = (low >> 16) & 0xff;
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return val ? val : -ENODATA;
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}
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EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, INTEL_TCC);
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/**
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* intel_tcc_get_offset() - returns the TCC Offset value to Tjmax
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* @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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*
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* Get the TCC offset value to Tjmax. The effective thermal throttling or TCC
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* activation temperature equals "Tjmax" - "TCC Offset", in degrees C.
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*
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* Return: Tcc offset value in degrees C on success, negative error code otherwise.
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*/
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int intel_tcc_get_offset(int cpu)
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{
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u32 low, high;
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int err;
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if (cpu < 0)
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err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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else
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err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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if (err)
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return err;
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return (low >> 24) & 0x3f;
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}
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EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, INTEL_TCC);
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/**
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* intel_tcc_set_offset() - set the TCC offset value to Tjmax
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* @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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* @offset: TCC offset value in degree C
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*
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* Set the TCC Offset value to Tjmax. The effective thermal throttling or TCC
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* activation temperature equals "Tjmax" - "TCC Offset", in degree C.
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*
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* Return: On success returns 0, negative error code otherwise.
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*/
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int intel_tcc_set_offset(int cpu, int offset)
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{
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u32 low, high;
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int err;
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if (offset < 0 || offset > 0x3f)
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return -EINVAL;
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if (cpu < 0)
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err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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else
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err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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if (err)
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return err;
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/* MSR Locked */
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if (low & BIT(31))
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return -EPERM;
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low &= ~(0x3f << 24);
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low |= offset << 24;
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if (cpu < 0)
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return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high);
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else
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return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high);
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}
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EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, INTEL_TCC);
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/**
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* intel_tcc_get_temp() - returns the current temperature
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* @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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* @temp: pointer to the memory for saving cpu temperature.
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* @pkg: true: Package Thermal Sensor. false: Core Thermal Sensor.
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*
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* Get the current temperature returned by the CPU core/package level
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* thermal sensor, in degrees C.
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*
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* Return: 0 on success, negative error code otherwise.
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*/
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int intel_tcc_get_temp(int cpu, int *temp, bool pkg)
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{
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u32 low, high;
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u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS;
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int tjmax, err;
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tjmax = intel_tcc_get_tjmax(cpu);
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if (tjmax < 0)
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return tjmax;
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if (cpu < 0)
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err = rdmsr_safe(msr, &low, &high);
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else
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err = rdmsr_safe_on_cpu(cpu, msr, &low, &high);
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if (err)
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return err;
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/* Temperature is beyond the valid thermal sensor range */
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if (!(low & BIT(31)))
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return -ENODATA;
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*temp = tjmax - ((low >> 16) & 0x7f);
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(intel_tcc_get_temp, INTEL_TCC);
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