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5745067177
The Versatile Express has 8 MB of dedicated video RAM (VRAM)
on the motherboard, which is what we should be using for the
PL111 if available. On this platform, the memory backplane
is constructed so that only this memory will work properly
with the CLCD on the motherboard, using any other memory
area just gives random snow on the display.
The CA9 Versatile Express also has a PL111 instance on its
core tile that can address all memory, and this does not
have the restriction.
The memory is assigned to the device using the memory-region
device tree property and a "shared-dma-pool" reserved
memory pool like this:
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vram: vram@48000000 {
compatible = "shared-dma-pool";
reg = <0x48000000 0x00800000>;
no-map;
};
};
clcd@1f000 {
compatible = "arm,pl111", "arm,primecell";
(...)
memory-region = <&vram>;
}·;
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180502134719.8388-2-linus.walleij@linaro.org
90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/*
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*
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* (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
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*
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*
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* Parts of this file were based on sources as follows:
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*
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* Copyright (c) 2006-2008 Intel Corporation
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* Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
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* Copyright (C) 2011 Texas Instruments
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms of
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* such GNU licence.
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*
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*/
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#ifndef _PL111_DRM_H_
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#define _PL111_DRM_H_
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#include <drm/drm_gem.h>
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#include <drm/drm_simple_kms_helper.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_bridge.h>
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#include <linux/clk-provider.h>
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#include <linux/interrupt.h>
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#define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
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struct drm_minor;
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/**
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* struct pl111_variant_data - encodes IP differences
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* @name: the name of this variant
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* @is_pl110: this is the early PL110 variant
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* @external_bgr: this is the Versatile Pl110 variant with external
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* BGR/RGB routing
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* @broken_clockdivider: the clock divider is broken and we need to
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* use the supplied clock directly
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* @broken_vblank: the vblank IRQ is broken on this variant
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* @formats: array of supported pixel formats on this variant
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* @nformats: the length of the array of supported pixel formats
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* @fb_bpp: desired bits per pixel on the default framebuffer
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*/
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struct pl111_variant_data {
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const char *name;
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bool is_pl110;
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bool external_bgr;
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bool broken_clockdivider;
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bool broken_vblank;
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const u32 *formats;
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unsigned int nformats;
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unsigned int fb_bpp;
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};
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struct pl111_drm_dev_private {
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struct drm_device *drm;
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struct drm_connector *connector;
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struct drm_panel *panel;
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struct drm_bridge *bridge;
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struct drm_simple_display_pipe pipe;
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void *regs;
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u32 memory_bw;
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u32 ienb;
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u32 ctrl;
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/* The pixel clock (a reference to our clock divider off of CLCDCLK). */
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struct clk *clk;
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/* pl111's internal clock divider. */
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struct clk_hw clk_div;
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/* Lock to sync access to CLCD_TIM2 between the common clock
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* subsystem and pl111_display_enable().
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*/
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spinlock_t tim2_lock;
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const struct pl111_variant_data *variant;
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void (*variant_display_enable) (struct drm_device *drm, u32 format);
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void (*variant_display_disable) (struct drm_device *drm);
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bool use_device_memory;
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};
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int pl111_display_init(struct drm_device *dev);
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irqreturn_t pl111_irq(int irq, void *data);
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int pl111_debugfs_init(struct drm_minor *minor);
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#endif /* _PL111_DRM_H_ */
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