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The patch below adds ARM ptrace functions to get the process load address. This is required for useful userspace debugging on mmuless systems. These values are obtained by reading magic offsets with PTRACE_PEEKUSR, as on other nommu targets. I picked arbitrary large values for the offsets. Signed-off-by: Paul Brook <paul@codesourcery.com>
185 lines
4.3 KiB
C
185 lines
4.3 KiB
C
/*
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* arch/arm/include/asm/ptrace.h
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*
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* Copyright (C) 1996-2003 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_PTRACE_H
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#define __ASM_ARM_PTRACE_H
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#include <asm/hwcap.h>
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#define PTRACE_GETREGS 12
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#define PTRACE_SETREGS 13
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#define PTRACE_GETFPREGS 14
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#define PTRACE_SETFPREGS 15
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/* PTRACE_ATTACH is 16 */
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/* PTRACE_DETACH is 17 */
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#define PTRACE_GETWMMXREGS 18
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#define PTRACE_SETWMMXREGS 19
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/* 20 is unused */
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#define PTRACE_OLDSETOPTIONS 21
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#define PTRACE_GET_THREAD_AREA 22
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#define PTRACE_SET_SYSCALL 23
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/* PTRACE_SYSCALL is 24 */
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#define PTRACE_GETCRUNCHREGS 25
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#define PTRACE_SETCRUNCHREGS 26
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#define PTRACE_GETVFPREGS 27
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#define PTRACE_SETVFPREGS 28
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/*
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* PSR bits
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*/
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#define USR26_MODE 0x00000000
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#define FIQ26_MODE 0x00000001
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#define IRQ26_MODE 0x00000002
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#define SVC26_MODE 0x00000003
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#define USR_MODE 0x00000010
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#define FIQ_MODE 0x00000011
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#define IRQ_MODE 0x00000012
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#define SVC_MODE 0x00000013
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#define ABT_MODE 0x00000017
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#define UND_MODE 0x0000001b
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#define SYSTEM_MODE 0x0000001f
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#define MODE32_BIT 0x00000010
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#define MODE_MASK 0x0000001f
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#define PSR_T_BIT 0x00000020
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#define PSR_F_BIT 0x00000040
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#define PSR_I_BIT 0x00000080
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#define PSR_A_BIT 0x00000100
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#define PSR_E_BIT 0x00000200
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#define PSR_J_BIT 0x01000000
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#define PSR_Q_BIT 0x08000000
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#define PSR_V_BIT 0x10000000
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#define PSR_C_BIT 0x20000000
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#define PSR_Z_BIT 0x40000000
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#define PSR_N_BIT 0x80000000
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/*
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* Groups of PSR bits
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*/
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#define PSR_f 0xff000000 /* Flags */
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#define PSR_s 0x00ff0000 /* Status */
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#define PSR_x 0x0000ff00 /* Extension */
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#define PSR_c 0x000000ff /* Control */
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/*
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* ARMv7 groups of APSR bits
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*/
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#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
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#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
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#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
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/*
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* Default endianness state
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*/
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#define PSR_ENDSTATE PSR_E_BIT
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#else
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#define PSR_ENDSTATE 0
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#endif
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/*
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* These are 'magic' values for PTRACE_PEEKUSR that return info about where a
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* process is located in memory.
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*/
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#define PT_TEXT_ADDR 0x10000
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#define PT_DATA_ADDR 0x10004
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#define PT_TEXT_END_ADDR 0x10008
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#ifndef __ASSEMBLY__
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/*
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* This struct defines the way the registers are stored on the
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* stack during a system call. Note that sizeof(struct pt_regs)
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* has to be a multiple of 8.
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*/
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struct pt_regs {
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long uregs[18];
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};
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#define ARM_cpsr uregs[16]
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#define ARM_pc uregs[15]
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#define ARM_lr uregs[14]
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#define ARM_sp uregs[13]
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#define ARM_ip uregs[12]
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#define ARM_fp uregs[11]
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#define ARM_r10 uregs[10]
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#define ARM_r9 uregs[9]
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#define ARM_r8 uregs[8]
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#define ARM_r7 uregs[7]
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#define ARM_r6 uregs[6]
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#define ARM_r5 uregs[5]
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#define ARM_r4 uregs[4]
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#define ARM_r3 uregs[3]
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#define ARM_r2 uregs[2]
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#define ARM_r1 uregs[1]
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#define ARM_r0 uregs[0]
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#define ARM_ORIG_r0 uregs[17]
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#ifdef __KERNEL__
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#define user_mode(regs) \
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(((regs)->ARM_cpsr & 0xf) == 0)
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#ifdef CONFIG_ARM_THUMB
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#define thumb_mode(regs) \
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(((regs)->ARM_cpsr & PSR_T_BIT))
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#else
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#define thumb_mode(regs) (0)
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#endif
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#define isa_mode(regs) \
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((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
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(((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
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#define processor_mode(regs) \
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((regs)->ARM_cpsr & MODE_MASK)
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#define interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & PSR_I_BIT))
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#define fast_interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & PSR_F_BIT))
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/* Are the current registers suitable for user mode?
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* (used to maintain security in signal handlers)
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*/
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static inline int valid_user_regs(struct pt_regs *regs)
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{
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if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
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regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
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return 1;
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}
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/*
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* Force CPSR to something logical...
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*/
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regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
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if (!(elf_hwcap & HWCAP_26BIT))
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regs->ARM_cpsr |= USR_MODE;
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return 0;
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}
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#define instruction_pointer(regs) (regs)->ARM_pc
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#ifdef CONFIG_SMP
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extern unsigned long profile_pc(struct pt_regs *regs);
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#else
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#define profile_pc(regs) instruction_pointer(regs)
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#endif
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#define predicate(x) ((x) & 0xf0000000)
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#define PREDICATE_ALWAYS 0xe0000000
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif
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