Adam Ford 89691775f5 drm: bridge: samsung-dsim: Dynamically configure DPHY timing ... The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. To facilitate this, we need to cache the hs_clock based on what is generated from the PLL. The phy_mipi_dphy_get_default_config_for_hsclk function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the hs_clk. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Michael Walle <michael@walle.cc> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # imx8mm-icore Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230526030559.326566-6-aford173@gmail.com		2023-05-26 09:20:41 +02:00
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analogix_dp.h	drm/bridge: analogix_dp: Split bind() into probe() and real bind()	2020-04-09 10:29:35 +02:00
dw_hdmi.h	drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver	2022-04-19 18:23:48 +02:00
dw_mipi_dsi.h	drm/bridge/synopsys: dsi: extend the prototype of mode_valid()	2022-01-04 12:53:59 +01:00
mhl.h	drm/bridge/mhl.h: Replace zero-length array with flexible-array member	2020-03-06 11:52:01 +01:00
samsung-dsim.h	drm: bridge: samsung-dsim: Dynamically configure DPHY timing	2023-05-26 09:20:41 +02:00