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2fe397a395
EtherAVB hardware requires 0 to be written to status register bits in order to clear them, however, care must be taken not to: 1. Clear other bits, by writing zero to them 2. Write one to reserved bits This patch corrects the ravb driver with respect to the second point above. This is done by defining reserved bit masks for the affected registers and, after auditing the code, ensure all sites that may write a one to a reserved bit use are suitably masked. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
349 lines
8.3 KiB
C
349 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* PTP 1588 clock using the Renesas Ethernet AVB
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*
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Renesas Solutions Corp.
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* Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
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*/
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#include "ravb.h"
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static int ravb_ptp_tcr_request(struct ravb_private *priv, u32 request)
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{
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struct net_device *ndev = priv->ndev;
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int error;
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error = ravb_wait(ndev, GCCR, GCCR_TCR, GCCR_TCR_NOREQ);
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if (error)
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return error;
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ravb_modify(ndev, GCCR, request, request);
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return ravb_wait(ndev, GCCR, GCCR_TCR, GCCR_TCR_NOREQ);
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}
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/* Caller must hold the lock */
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static int ravb_ptp_time_read(struct ravb_private *priv, struct timespec64 *ts)
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{
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struct net_device *ndev = priv->ndev;
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int error;
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error = ravb_ptp_tcr_request(priv, GCCR_TCR_CAPTURE);
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if (error)
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return error;
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ts->tv_nsec = ravb_read(ndev, GCT0);
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ts->tv_sec = ravb_read(ndev, GCT1) |
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((s64)ravb_read(ndev, GCT2) << 32);
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return 0;
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}
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/* Caller must hold the lock */
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static int ravb_ptp_time_write(struct ravb_private *priv,
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const struct timespec64 *ts)
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{
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struct net_device *ndev = priv->ndev;
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int error;
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u32 gccr;
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error = ravb_ptp_tcr_request(priv, GCCR_TCR_RESET);
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if (error)
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return error;
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gccr = ravb_read(ndev, GCCR);
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if (gccr & GCCR_LTO)
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return -EBUSY;
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ravb_write(ndev, ts->tv_nsec, GTO0);
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ravb_write(ndev, ts->tv_sec, GTO1);
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ravb_write(ndev, (ts->tv_sec >> 32) & 0xffff, GTO2);
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ravb_write(ndev, gccr | GCCR_LTO, GCCR);
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return 0;
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}
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/* Caller must hold the lock */
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static int ravb_ptp_update_compare(struct ravb_private *priv, u32 ns)
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{
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struct net_device *ndev = priv->ndev;
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/* When the comparison value (GPTC.PTCV) is in range of
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* [x-1 to x+1] (x is the configured increment value in
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* GTI.TIV), it may happen that a comparison match is
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* not detected when the timer wraps around.
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*/
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u32 gti_ns_plus_1 = (priv->ptp.current_addend >> 20) + 1;
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u32 gccr;
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if (ns < gti_ns_plus_1)
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ns = gti_ns_plus_1;
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else if (ns > 0 - gti_ns_plus_1)
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ns = 0 - gti_ns_plus_1;
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gccr = ravb_read(ndev, GCCR);
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if (gccr & GCCR_LPTC)
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return -EBUSY;
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ravb_write(ndev, ns, GPTC);
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ravb_write(ndev, gccr | GCCR_LPTC, GCCR);
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return 0;
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}
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/* PTP clock operations */
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static int ravb_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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struct ravb_private *priv = container_of(ptp, struct ravb_private,
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ptp.info);
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struct net_device *ndev = priv->ndev;
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unsigned long flags;
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u32 diff, addend;
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bool neg_adj = false;
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u32 gccr;
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if (ppb < 0) {
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neg_adj = true;
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ppb = -ppb;
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}
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addend = priv->ptp.default_addend;
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diff = div_u64((u64)addend * ppb, NSEC_PER_SEC);
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addend = neg_adj ? addend - diff : addend + diff;
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spin_lock_irqsave(&priv->lock, flags);
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priv->ptp.current_addend = addend;
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gccr = ravb_read(ndev, GCCR);
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if (gccr & GCCR_LTI) {
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spin_unlock_irqrestore(&priv->lock, flags);
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return -EBUSY;
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}
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ravb_write(ndev, addend & GTI_TIV, GTI);
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ravb_write(ndev, gccr | GCCR_LTI, GCCR);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int ravb_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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struct ravb_private *priv = container_of(ptp, struct ravb_private,
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ptp.info);
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struct timespec64 ts;
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unsigned long flags;
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int error;
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spin_lock_irqsave(&priv->lock, flags);
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error = ravb_ptp_time_read(priv, &ts);
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if (!error) {
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u64 now = ktime_to_ns(timespec64_to_ktime(ts));
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ts = ns_to_timespec64(now + delta);
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error = ravb_ptp_time_write(priv, &ts);
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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return error;
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}
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static int ravb_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts)
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{
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struct ravb_private *priv = container_of(ptp, struct ravb_private,
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ptp.info);
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unsigned long flags;
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int error;
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spin_lock_irqsave(&priv->lock, flags);
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error = ravb_ptp_time_read(priv, ts);
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spin_unlock_irqrestore(&priv->lock, flags);
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return error;
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}
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static int ravb_ptp_settime64(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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struct ravb_private *priv = container_of(ptp, struct ravb_private,
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ptp.info);
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unsigned long flags;
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int error;
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spin_lock_irqsave(&priv->lock, flags);
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error = ravb_ptp_time_write(priv, ts);
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spin_unlock_irqrestore(&priv->lock, flags);
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return error;
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}
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static int ravb_ptp_extts(struct ptp_clock_info *ptp,
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struct ptp_extts_request *req, int on)
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{
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struct ravb_private *priv = container_of(ptp, struct ravb_private,
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ptp.info);
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struct net_device *ndev = priv->ndev;
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unsigned long flags;
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if (req->index)
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return -EINVAL;
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if (priv->ptp.extts[req->index] == on)
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return 0;
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priv->ptp.extts[req->index] = on;
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spin_lock_irqsave(&priv->lock, flags);
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if (priv->chip_id == RCAR_GEN2)
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ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0);
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else if (on)
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ravb_write(ndev, GIE_PTCS, GIE);
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else
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ravb_write(ndev, GID_PTCD, GID);
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mmiowb();
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int ravb_ptp_perout(struct ptp_clock_info *ptp,
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struct ptp_perout_request *req, int on)
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{
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struct ravb_private *priv = container_of(ptp, struct ravb_private,
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ptp.info);
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struct net_device *ndev = priv->ndev;
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struct ravb_ptp_perout *perout;
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unsigned long flags;
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int error = 0;
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if (req->index)
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return -EINVAL;
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if (on) {
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u64 start_ns;
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u64 period_ns;
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start_ns = req->start.sec * NSEC_PER_SEC + req->start.nsec;
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period_ns = req->period.sec * NSEC_PER_SEC + req->period.nsec;
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if (start_ns > U32_MAX) {
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netdev_warn(ndev,
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"ptp: start value (nsec) is over limit. Maximum size of start is only 32 bits\n");
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return -ERANGE;
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}
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if (period_ns > U32_MAX) {
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netdev_warn(ndev,
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"ptp: period value (nsec) is over limit. Maximum size of period is only 32 bits\n");
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return -ERANGE;
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}
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spin_lock_irqsave(&priv->lock, flags);
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perout = &priv->ptp.perout[req->index];
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perout->target = (u32)start_ns;
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perout->period = (u32)period_ns;
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error = ravb_ptp_update_compare(priv, (u32)start_ns);
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if (!error) {
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/* Unmask interrupt */
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if (priv->chip_id == RCAR_GEN2)
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ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME);
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else
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ravb_write(ndev, GIE_PTMS0, GIE);
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}
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} else {
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spin_lock_irqsave(&priv->lock, flags);
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perout = &priv->ptp.perout[req->index];
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perout->period = 0;
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/* Mask interrupt */
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if (priv->chip_id == RCAR_GEN2)
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ravb_modify(ndev, GIC, GIC_PTME, 0);
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else
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ravb_write(ndev, GID_PTMD0, GID);
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}
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mmiowb();
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spin_unlock_irqrestore(&priv->lock, flags);
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return error;
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}
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static int ravb_ptp_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *req, int on)
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{
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switch (req->type) {
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case PTP_CLK_REQ_EXTTS:
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return ravb_ptp_extts(ptp, &req->extts, on);
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case PTP_CLK_REQ_PEROUT:
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return ravb_ptp_perout(ptp, &req->perout, on);
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default:
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return -EOPNOTSUPP;
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}
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}
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static const struct ptp_clock_info ravb_ptp_info = {
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.owner = THIS_MODULE,
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.name = "ravb clock",
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.max_adj = 50000000,
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.n_ext_ts = N_EXT_TS,
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.n_per_out = N_PER_OUT,
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.adjfreq = ravb_ptp_adjfreq,
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.adjtime = ravb_ptp_adjtime,
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.gettime64 = ravb_ptp_gettime64,
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.settime64 = ravb_ptp_settime64,
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.enable = ravb_ptp_enable,
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};
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/* Caller must hold the lock */
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void ravb_ptp_interrupt(struct net_device *ndev)
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{
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struct ravb_private *priv = netdev_priv(ndev);
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u32 gis = ravb_read(ndev, GIS);
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gis &= ravb_read(ndev, GIC);
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if (gis & GIS_PTCF) {
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struct ptp_clock_event event;
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event.type = PTP_CLOCK_EXTTS;
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event.index = 0;
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event.timestamp = ravb_read(ndev, GCPT);
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ptp_clock_event(priv->ptp.clock, &event);
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}
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if (gis & GIS_PTMF) {
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struct ravb_ptp_perout *perout = priv->ptp.perout;
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if (perout->period) {
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perout->target += perout->period;
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ravb_ptp_update_compare(priv, perout->target);
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}
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}
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ravb_write(ndev, ~(gis | GIS_RESERVED), GIS);
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}
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void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev)
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{
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struct ravb_private *priv = netdev_priv(ndev);
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unsigned long flags;
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priv->ptp.info = ravb_ptp_info;
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priv->ptp.default_addend = ravb_read(ndev, GTI);
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priv->ptp.current_addend = priv->ptp.default_addend;
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spin_lock_irqsave(&priv->lock, flags);
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ravb_wait(ndev, GCCR, GCCR_TCR, GCCR_TCR_NOREQ);
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ravb_modify(ndev, GCCR, GCCR_TCSS, GCCR_TCSS_ADJGPTP);
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mmiowb();
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spin_unlock_irqrestore(&priv->lock, flags);
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priv->ptp.clock = ptp_clock_register(&priv->ptp.info, &pdev->dev);
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}
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void ravb_ptp_stop(struct net_device *ndev)
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{
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struct ravb_private *priv = netdev_priv(ndev);
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ravb_write(ndev, 0, GIC);
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ravb_write(ndev, 0, GIS);
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ptp_clock_unregister(priv->ptp.clock);
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}
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