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d632e86435
Add a comment to the bypass field based on the commit b997e3edca
("pwm: lpss: Set enable-bit before waiting for update-bit
to go low").
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Low Power Subsystem PWM controller driver
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*
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* Copyright (C) 2014, Intel Corporation
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*
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* Derived from the original pwm-lpss.c
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*/
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#ifndef __PWM_LPSS_H
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#define __PWM_LPSS_H
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#include <linux/device.h>
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#include <linux/pwm.h>
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#define MAX_PWMS 4
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struct pwm_lpss_chip {
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struct pwm_chip chip;
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void __iomem *regs;
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const struct pwm_lpss_boardinfo *info;
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};
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struct pwm_lpss_boardinfo {
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unsigned long clk_rate;
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unsigned int npwm;
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unsigned long base_unit_bits;
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/*
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* Some versions of the IP may stuck in the state machine if enable
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* bit is not set, and hence update bit will show busy status till
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* the reset. For the rest it may be otherwise.
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*/
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bool bypass;
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/*
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* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
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* messes with the PWM0 controllers state,
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*/
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bool other_devices_aml_touches_pwm_regs;
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};
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extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
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extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;
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extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info;
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extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info;
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struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
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const struct pwm_lpss_boardinfo *info);
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#endif /* __PWM_LPSS_H */
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