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e605b743f3
Enable IB ULPs to use a larger portion of the device EQs (which map to IRQs). The mlx4_ib driver follows the mlx4_core framework of the EQs to be divided among the device ports. In this scheme, for each IB port, the number of allocated EQs follows the number of cores, subject to other system constraints, such as number available MSI-X vectors. Signed-off-by: Shlomo Pongratz <shlomop@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
829 lines
20 KiB
C
829 lines
20 KiB
C
/*
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* Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
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* Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/mlx4/cq.h>
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#include <linux/mlx4/qp.h>
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#include <linux/slab.h>
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#include "mlx4_ib.h"
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#include "user.h"
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static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
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{
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struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
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ibcq->comp_handler(ibcq, ibcq->cq_context);
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}
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static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
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{
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struct ib_event event;
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struct ib_cq *ibcq;
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if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
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pr_warn("Unexpected event type %d "
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"on CQ %06x\n", type, cq->cqn);
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return;
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}
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ibcq = &to_mibcq(cq)->ibcq;
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if (ibcq->event_handler) {
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event.device = ibcq->device;
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event.event = IB_EVENT_CQ_ERR;
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event.element.cq = ibcq;
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ibcq->event_handler(&event, ibcq->cq_context);
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}
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}
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static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
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{
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return mlx4_buf_offset(&buf->buf, n * sizeof (struct mlx4_cqe));
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}
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static void *get_cqe(struct mlx4_ib_cq *cq, int n)
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{
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return get_cqe_from_buf(&cq->buf, n);
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}
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static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
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{
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struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
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return (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
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!!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
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}
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static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
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{
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return get_sw_cqe(cq, cq->mcq.cons_index);
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}
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int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
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{
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struct mlx4_ib_cq *mcq = to_mcq(cq);
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struct mlx4_ib_dev *dev = to_mdev(cq->device);
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return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
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}
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static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
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{
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int err;
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err = mlx4_buf_alloc(dev->dev, nent * sizeof(struct mlx4_cqe),
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PAGE_SIZE * 2, &buf->buf);
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if (err)
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goto out;
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err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
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&buf->mtt);
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if (err)
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goto err_buf;
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err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf);
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if (err)
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goto err_mtt;
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return 0;
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err_mtt:
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mlx4_mtt_cleanup(dev->dev, &buf->mtt);
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err_buf:
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mlx4_buf_free(dev->dev, nent * sizeof(struct mlx4_cqe),
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&buf->buf);
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out:
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return err;
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}
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static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
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{
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mlx4_buf_free(dev->dev, (cqe + 1) * sizeof(struct mlx4_cqe), &buf->buf);
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}
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static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
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struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
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u64 buf_addr, int cqe)
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{
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int err;
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*umem = ib_umem_get(context, buf_addr, cqe * sizeof (struct mlx4_cqe),
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IB_ACCESS_LOCAL_WRITE, 1);
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if (IS_ERR(*umem))
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return PTR_ERR(*umem);
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err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
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ilog2((*umem)->page_size), &buf->mtt);
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if (err)
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goto err_buf;
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err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
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if (err)
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goto err_mtt;
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return 0;
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err_mtt:
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mlx4_mtt_cleanup(dev->dev, &buf->mtt);
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err_buf:
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ib_umem_release(*umem);
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return err;
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}
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struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
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struct ib_ucontext *context,
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struct ib_udata *udata)
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{
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struct mlx4_ib_dev *dev = to_mdev(ibdev);
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struct mlx4_ib_cq *cq;
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struct mlx4_uar *uar;
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int err;
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if (entries < 1 || entries > dev->dev->caps.max_cqes)
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return ERR_PTR(-EINVAL);
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cq = kmalloc(sizeof *cq, GFP_KERNEL);
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if (!cq)
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return ERR_PTR(-ENOMEM);
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entries = roundup_pow_of_two(entries + 1);
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cq->ibcq.cqe = entries - 1;
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mutex_init(&cq->resize_mutex);
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spin_lock_init(&cq->lock);
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cq->resize_buf = NULL;
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cq->resize_umem = NULL;
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if (context) {
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struct mlx4_ib_create_cq ucmd;
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if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
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err = -EFAULT;
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goto err_cq;
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}
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err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
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ucmd.buf_addr, entries);
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if (err)
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goto err_cq;
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err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
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&cq->db);
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if (err)
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goto err_mtt;
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uar = &to_mucontext(context)->uar;
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} else {
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err = mlx4_db_alloc(dev->dev, &cq->db, 1);
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if (err)
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goto err_cq;
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cq->mcq.set_ci_db = cq->db.db;
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cq->mcq.arm_db = cq->db.db + 1;
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*cq->mcq.set_ci_db = 0;
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*cq->mcq.arm_db = 0;
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err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
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if (err)
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goto err_db;
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uar = &dev->priv_uar;
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}
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if (dev->eq_table)
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vector = dev->eq_table[vector % ibdev->num_comp_vectors];
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err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
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cq->db.dma, &cq->mcq, vector, 0);
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if (err)
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goto err_dbmap;
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cq->mcq.comp = mlx4_ib_cq_comp;
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cq->mcq.event = mlx4_ib_cq_event;
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if (context)
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if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
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err = -EFAULT;
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goto err_dbmap;
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}
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return &cq->ibcq;
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err_dbmap:
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if (context)
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mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
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err_mtt:
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mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
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if (context)
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ib_umem_release(cq->umem);
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else
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mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
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err_db:
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if (!context)
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mlx4_db_free(dev->dev, &cq->db);
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err_cq:
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kfree(cq);
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return ERR_PTR(err);
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}
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static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
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int entries)
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{
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int err;
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if (cq->resize_buf)
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return -EBUSY;
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cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
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if (!cq->resize_buf)
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return -ENOMEM;
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err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
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if (err) {
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kfree(cq->resize_buf);
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cq->resize_buf = NULL;
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return err;
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}
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cq->resize_buf->cqe = entries - 1;
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return 0;
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}
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static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
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int entries, struct ib_udata *udata)
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{
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struct mlx4_ib_resize_cq ucmd;
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int err;
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if (cq->resize_umem)
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return -EBUSY;
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if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
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return -EFAULT;
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cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
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if (!cq->resize_buf)
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return -ENOMEM;
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err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
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&cq->resize_umem, ucmd.buf_addr, entries);
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if (err) {
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kfree(cq->resize_buf);
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cq->resize_buf = NULL;
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return err;
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}
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cq->resize_buf->cqe = entries - 1;
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return 0;
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}
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static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
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{
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u32 i;
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i = cq->mcq.cons_index;
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while (get_sw_cqe(cq, i & cq->ibcq.cqe))
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++i;
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return i - cq->mcq.cons_index;
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}
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static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
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{
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struct mlx4_cqe *cqe, *new_cqe;
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int i;
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i = cq->mcq.cons_index;
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cqe = get_cqe(cq, i & cq->ibcq.cqe);
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while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
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new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
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(i + 1) & cq->resize_buf->cqe);
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memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), sizeof(struct mlx4_cqe));
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new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
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(((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
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cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
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}
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++cq->mcq.cons_index;
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}
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int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
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{
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struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
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struct mlx4_ib_cq *cq = to_mcq(ibcq);
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struct mlx4_mtt mtt;
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int outst_cqe;
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int err;
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mutex_lock(&cq->resize_mutex);
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if (entries < 1 || entries > dev->dev->caps.max_cqes) {
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err = -EINVAL;
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goto out;
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}
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entries = roundup_pow_of_two(entries + 1);
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if (entries == ibcq->cqe + 1) {
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err = 0;
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goto out;
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}
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if (ibcq->uobject) {
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err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
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if (err)
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goto out;
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} else {
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/* Can't be smaller than the number of outstanding CQEs */
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outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
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if (entries < outst_cqe + 1) {
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err = 0;
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goto out;
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}
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err = mlx4_alloc_resize_buf(dev, cq, entries);
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if (err)
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goto out;
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}
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mtt = cq->buf.mtt;
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err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
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if (err)
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goto err_buf;
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mlx4_mtt_cleanup(dev->dev, &mtt);
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if (ibcq->uobject) {
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cq->buf = cq->resize_buf->buf;
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cq->ibcq.cqe = cq->resize_buf->cqe;
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ib_umem_release(cq->umem);
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cq->umem = cq->resize_umem;
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kfree(cq->resize_buf);
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cq->resize_buf = NULL;
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cq->resize_umem = NULL;
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} else {
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struct mlx4_ib_cq_buf tmp_buf;
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int tmp_cqe = 0;
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spin_lock_irq(&cq->lock);
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if (cq->resize_buf) {
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mlx4_ib_cq_resize_copy_cqes(cq);
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tmp_buf = cq->buf;
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tmp_cqe = cq->ibcq.cqe;
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cq->buf = cq->resize_buf->buf;
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cq->ibcq.cqe = cq->resize_buf->cqe;
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|
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kfree(cq->resize_buf);
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cq->resize_buf = NULL;
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}
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spin_unlock_irq(&cq->lock);
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|
|
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if (tmp_cqe)
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mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
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}
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goto out;
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|
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err_buf:
|
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mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
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if (!ibcq->uobject)
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mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
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cq->resize_buf->cqe);
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|
|
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kfree(cq->resize_buf);
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cq->resize_buf = NULL;
|
|
|
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if (cq->resize_umem) {
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ib_umem_release(cq->resize_umem);
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cq->resize_umem = NULL;
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}
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|
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out:
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mutex_unlock(&cq->resize_mutex);
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return err;
|
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}
|
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|
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int mlx4_ib_destroy_cq(struct ib_cq *cq)
|
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{
|
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struct mlx4_ib_dev *dev = to_mdev(cq->device);
|
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struct mlx4_ib_cq *mcq = to_mcq(cq);
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|
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mlx4_cq_free(dev->dev, &mcq->mcq);
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mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
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|
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if (cq->uobject) {
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mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
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ib_umem_release(mcq->umem);
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} else {
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mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
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mlx4_db_free(dev->dev, &mcq->db);
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}
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|
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kfree(mcq);
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|
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return 0;
|
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}
|
|
|
|
static void dump_cqe(void *cqe)
|
|
{
|
|
__be32 *buf = cqe;
|
|
|
|
pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
|
|
be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
|
|
be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
|
|
be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
|
|
}
|
|
|
|
static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
|
|
struct ib_wc *wc)
|
|
{
|
|
if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
|
|
pr_debug("local QP operation err "
|
|
"(QPN %06x, WQE index %x, vendor syndrome %02x, "
|
|
"opcode = %02x)\n",
|
|
be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
|
|
cqe->vendor_err_syndrome,
|
|
cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
|
|
dump_cqe(cqe);
|
|
}
|
|
|
|
switch (cqe->syndrome) {
|
|
case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
|
|
wc->status = IB_WC_LOC_LEN_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
|
|
wc->status = IB_WC_LOC_QP_OP_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
|
|
wc->status = IB_WC_LOC_PROT_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
|
|
wc->status = IB_WC_WR_FLUSH_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_MW_BIND_ERR:
|
|
wc->status = IB_WC_MW_BIND_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
|
|
wc->status = IB_WC_BAD_RESP_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
|
|
wc->status = IB_WC_LOC_ACCESS_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
|
|
wc->status = IB_WC_REM_INV_REQ_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
|
|
wc->status = IB_WC_REM_ACCESS_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
|
|
wc->status = IB_WC_REM_OP_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
|
|
wc->status = IB_WC_RETRY_EXC_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
|
|
wc->status = IB_WC_RNR_RETRY_EXC_ERR;
|
|
break;
|
|
case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
|
|
wc->status = IB_WC_REM_ABORT_ERR;
|
|
break;
|
|
default:
|
|
wc->status = IB_WC_GENERAL_ERR;
|
|
break;
|
|
}
|
|
|
|
wc->vendor_err = cqe->vendor_err_syndrome;
|
|
}
|
|
|
|
static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
|
|
{
|
|
return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
|
|
MLX4_CQE_STATUS_IPV4F |
|
|
MLX4_CQE_STATUS_IPV4OPT |
|
|
MLX4_CQE_STATUS_IPV6 |
|
|
MLX4_CQE_STATUS_IPOK)) ==
|
|
cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
|
|
MLX4_CQE_STATUS_IPOK)) &&
|
|
(status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
|
|
MLX4_CQE_STATUS_TCP)) &&
|
|
checksum == cpu_to_be16(0xffff);
|
|
}
|
|
|
|
static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
|
|
struct mlx4_ib_qp **cur_qp,
|
|
struct ib_wc *wc)
|
|
{
|
|
struct mlx4_cqe *cqe;
|
|
struct mlx4_qp *mqp;
|
|
struct mlx4_ib_wq *wq;
|
|
struct mlx4_ib_srq *srq;
|
|
int is_send;
|
|
int is_error;
|
|
u32 g_mlpath_rqpn;
|
|
u16 wqe_ctr;
|
|
|
|
repoll:
|
|
cqe = next_cqe_sw(cq);
|
|
if (!cqe)
|
|
return -EAGAIN;
|
|
|
|
++cq->mcq.cons_index;
|
|
|
|
/*
|
|
* Make sure we read CQ entry contents after we've checked the
|
|
* ownership bit.
|
|
*/
|
|
rmb();
|
|
|
|
is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
|
|
is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
|
|
MLX4_CQE_OPCODE_ERROR;
|
|
|
|
if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
|
|
is_send)) {
|
|
pr_warn("Completion for NOP opcode detected!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Resize CQ in progress */
|
|
if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
|
|
if (cq->resize_buf) {
|
|
struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
|
|
|
|
mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
|
|
cq->buf = cq->resize_buf->buf;
|
|
cq->ibcq.cqe = cq->resize_buf->cqe;
|
|
|
|
kfree(cq->resize_buf);
|
|
cq->resize_buf = NULL;
|
|
}
|
|
|
|
goto repoll;
|
|
}
|
|
|
|
if (!*cur_qp ||
|
|
(be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
|
|
/*
|
|
* We do not have to take the QP table lock here,
|
|
* because CQs will be locked while QPs are removed
|
|
* from the table.
|
|
*/
|
|
mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
|
|
be32_to_cpu(cqe->vlan_my_qpn));
|
|
if (unlikely(!mqp)) {
|
|
pr_warn("CQ %06x with entry for unknown QPN %06x\n",
|
|
cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
|
|
return -EINVAL;
|
|
}
|
|
|
|
*cur_qp = to_mibqp(mqp);
|
|
}
|
|
|
|
wc->qp = &(*cur_qp)->ibqp;
|
|
|
|
if (is_send) {
|
|
wq = &(*cur_qp)->sq;
|
|
if (!(*cur_qp)->sq_signal_bits) {
|
|
wqe_ctr = be16_to_cpu(cqe->wqe_index);
|
|
wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
|
|
}
|
|
wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
|
|
++wq->tail;
|
|
} else if ((*cur_qp)->ibqp.srq) {
|
|
srq = to_msrq((*cur_qp)->ibqp.srq);
|
|
wqe_ctr = be16_to_cpu(cqe->wqe_index);
|
|
wc->wr_id = srq->wrid[wqe_ctr];
|
|
mlx4_ib_free_srq_wqe(srq, wqe_ctr);
|
|
} else {
|
|
wq = &(*cur_qp)->rq;
|
|
wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
|
|
++wq->tail;
|
|
}
|
|
|
|
if (unlikely(is_error)) {
|
|
mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
|
|
return 0;
|
|
}
|
|
|
|
wc->status = IB_WC_SUCCESS;
|
|
|
|
if (is_send) {
|
|
wc->wc_flags = 0;
|
|
switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
|
|
case MLX4_OPCODE_RDMA_WRITE_IMM:
|
|
wc->wc_flags |= IB_WC_WITH_IMM;
|
|
case MLX4_OPCODE_RDMA_WRITE:
|
|
wc->opcode = IB_WC_RDMA_WRITE;
|
|
break;
|
|
case MLX4_OPCODE_SEND_IMM:
|
|
wc->wc_flags |= IB_WC_WITH_IMM;
|
|
case MLX4_OPCODE_SEND:
|
|
case MLX4_OPCODE_SEND_INVAL:
|
|
wc->opcode = IB_WC_SEND;
|
|
break;
|
|
case MLX4_OPCODE_RDMA_READ:
|
|
wc->opcode = IB_WC_RDMA_READ;
|
|
wc->byte_len = be32_to_cpu(cqe->byte_cnt);
|
|
break;
|
|
case MLX4_OPCODE_ATOMIC_CS:
|
|
wc->opcode = IB_WC_COMP_SWAP;
|
|
wc->byte_len = 8;
|
|
break;
|
|
case MLX4_OPCODE_ATOMIC_FA:
|
|
wc->opcode = IB_WC_FETCH_ADD;
|
|
wc->byte_len = 8;
|
|
break;
|
|
case MLX4_OPCODE_MASKED_ATOMIC_CS:
|
|
wc->opcode = IB_WC_MASKED_COMP_SWAP;
|
|
wc->byte_len = 8;
|
|
break;
|
|
case MLX4_OPCODE_MASKED_ATOMIC_FA:
|
|
wc->opcode = IB_WC_MASKED_FETCH_ADD;
|
|
wc->byte_len = 8;
|
|
break;
|
|
case MLX4_OPCODE_BIND_MW:
|
|
wc->opcode = IB_WC_BIND_MW;
|
|
break;
|
|
case MLX4_OPCODE_LSO:
|
|
wc->opcode = IB_WC_LSO;
|
|
break;
|
|
case MLX4_OPCODE_FMR:
|
|
wc->opcode = IB_WC_FAST_REG_MR;
|
|
break;
|
|
case MLX4_OPCODE_LOCAL_INVAL:
|
|
wc->opcode = IB_WC_LOCAL_INV;
|
|
break;
|
|
}
|
|
} else {
|
|
wc->byte_len = be32_to_cpu(cqe->byte_cnt);
|
|
|
|
switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
|
|
case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
|
|
wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
|
|
wc->wc_flags = IB_WC_WITH_IMM;
|
|
wc->ex.imm_data = cqe->immed_rss_invalid;
|
|
break;
|
|
case MLX4_RECV_OPCODE_SEND_INVAL:
|
|
wc->opcode = IB_WC_RECV;
|
|
wc->wc_flags = IB_WC_WITH_INVALIDATE;
|
|
wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
|
|
break;
|
|
case MLX4_RECV_OPCODE_SEND:
|
|
wc->opcode = IB_WC_RECV;
|
|
wc->wc_flags = 0;
|
|
break;
|
|
case MLX4_RECV_OPCODE_SEND_IMM:
|
|
wc->opcode = IB_WC_RECV;
|
|
wc->wc_flags = IB_WC_WITH_IMM;
|
|
wc->ex.imm_data = cqe->immed_rss_invalid;
|
|
break;
|
|
}
|
|
|
|
wc->slid = be16_to_cpu(cqe->rlid);
|
|
g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
|
|
wc->src_qp = g_mlpath_rqpn & 0xffffff;
|
|
wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
|
|
wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
|
|
wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
|
|
wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status,
|
|
cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
|
|
if (rdma_port_get_link_layer(wc->qp->device,
|
|
(*cur_qp)->port) == IB_LINK_LAYER_ETHERNET)
|
|
wc->sl = be16_to_cpu(cqe->sl_vid) >> 13;
|
|
else
|
|
wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
|
|
{
|
|
struct mlx4_ib_cq *cq = to_mcq(ibcq);
|
|
struct mlx4_ib_qp *cur_qp = NULL;
|
|
unsigned long flags;
|
|
int npolled;
|
|
int err = 0;
|
|
|
|
spin_lock_irqsave(&cq->lock, flags);
|
|
|
|
for (npolled = 0; npolled < num_entries; ++npolled) {
|
|
err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
|
|
if (err)
|
|
break;
|
|
}
|
|
|
|
mlx4_cq_set_ci(&cq->mcq);
|
|
|
|
spin_unlock_irqrestore(&cq->lock, flags);
|
|
|
|
if (err == 0 || err == -EAGAIN)
|
|
return npolled;
|
|
else
|
|
return err;
|
|
}
|
|
|
|
int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
|
|
{
|
|
mlx4_cq_arm(&to_mcq(ibcq)->mcq,
|
|
(flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
|
|
MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
|
|
to_mdev(ibcq->device)->uar_map,
|
|
MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
|
|
{
|
|
u32 prod_index;
|
|
int nfreed = 0;
|
|
struct mlx4_cqe *cqe, *dest;
|
|
u8 owner_bit;
|
|
|
|
/*
|
|
* First we need to find the current producer index, so we
|
|
* know where to start cleaning from. It doesn't matter if HW
|
|
* adds new entries after this loop -- the QP we're worried
|
|
* about is already in RESET, so the new entries won't come
|
|
* from our QP and therefore don't need to be checked.
|
|
*/
|
|
for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
|
|
if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
|
|
break;
|
|
|
|
/*
|
|
* Now sweep backwards through the CQ, removing CQ entries
|
|
* that match our QP by copying older entries on top of them.
|
|
*/
|
|
while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
|
|
cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
|
|
if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
|
|
if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
|
|
mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
|
|
++nfreed;
|
|
} else if (nfreed) {
|
|
dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
|
|
owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
|
|
memcpy(dest, cqe, sizeof *cqe);
|
|
dest->owner_sr_opcode = owner_bit |
|
|
(dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
|
|
}
|
|
}
|
|
|
|
if (nfreed) {
|
|
cq->mcq.cons_index += nfreed;
|
|
/*
|
|
* Make sure update of buffer contents is done before
|
|
* updating consumer index.
|
|
*/
|
|
wmb();
|
|
mlx4_cq_set_ci(&cq->mcq);
|
|
}
|
|
}
|
|
|
|
void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
|
|
{
|
|
spin_lock_irq(&cq->lock);
|
|
__mlx4_ib_cq_clean(cq, qpn, srq);
|
|
spin_unlock_irq(&cq->lock);
|
|
}
|