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4135b7f8d4
Assume that if the oscillator is enabled (OSC32EN bit is present), the delay has already elapsed as the bootloader probably waited for the oscillator to settle. This could waste up to 1.2s. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
520 lines
12 KiB
C
520 lines
12 KiB
C
/*
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* drivers/clk/at91/sckc.c
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#define SLOW_CLOCK_FREQ 32768
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#define SLOWCK_SW_CYCLES 5
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#define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
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SLOW_CLOCK_FREQ)
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#define AT91_SCKC_CR 0x00
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#define AT91_SCKC_RCEN (1 << 0)
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#define AT91_SCKC_OSC32EN (1 << 1)
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#define AT91_SCKC_OSC32BYP (1 << 2)
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#define AT91_SCKC_OSCSEL (1 << 3)
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struct clk_slow_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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unsigned long startup_usec;
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};
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#define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw)
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struct clk_sama5d4_slow_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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unsigned long startup_usec;
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bool prepared;
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};
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#define to_clk_sama5d4_slow_osc(hw) container_of(hw, struct clk_sama5d4_slow_osc, hw)
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struct clk_slow_rc_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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unsigned long frequency;
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unsigned long accuracy;
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unsigned long startup_usec;
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};
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#define to_clk_slow_rc_osc(hw) container_of(hw, struct clk_slow_rc_osc, hw)
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struct clk_sam9x5_slow {
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struct clk_hw hw;
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void __iomem *sckcr;
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u8 parent;
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};
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#define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
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static int clk_slow_osc_prepare(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & (AT91_SCKC_OSC32BYP | AT91_SCKC_OSC32EN))
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return 0;
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writel(tmp | AT91_SCKC_OSC32EN, sckcr);
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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return 0;
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}
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static void clk_slow_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & AT91_SCKC_OSC32BYP)
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return;
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writel(tmp & ~AT91_SCKC_OSC32EN, sckcr);
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}
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static int clk_slow_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & AT91_SCKC_OSC32BYP)
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return 1;
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return !!(tmp & AT91_SCKC_OSC32EN);
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}
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static const struct clk_ops slow_osc_ops = {
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.prepare = clk_slow_osc_prepare,
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.unprepare = clk_slow_osc_unprepare,
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.is_prepared = clk_slow_osc_is_prepared,
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};
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static struct clk_hw * __init
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at91_clk_register_slow_osc(void __iomem *sckcr,
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const char *name,
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const char *parent_name,
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unsigned long startup,
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bool bypass)
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{
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struct clk_slow_osc *osc;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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if (!sckcr || !name || !parent_name)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &slow_osc_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->sckcr = sckcr;
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osc->startup_usec = startup;
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if (bypass)
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writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP,
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sckcr);
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hw = &osc->hw;
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ret = clk_hw_register(NULL, &osc->hw);
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if (ret) {
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kfree(osc);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void __init
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of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr)
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{
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struct clk_hw *hw;
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const char *parent_name;
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const char *name = np->name;
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u32 startup;
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bool bypass;
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parent_name = of_clk_get_parent_name(np, 0);
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of_property_read_string(np, "clock-output-names", &name);
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of_property_read_u32(np, "atmel,startup-time-usec", &startup);
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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hw = at91_clk_register_slow_osc(sckcr, name, parent_name, startup,
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bypass);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return osc->frequency;
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}
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static unsigned long clk_slow_rc_osc_recalc_accuracy(struct clk_hw *hw,
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unsigned long parent_acc)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return osc->accuracy;
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}
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static int clk_slow_rc_osc_prepare(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr);
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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return 0;
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}
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static void clk_slow_rc_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr);
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}
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static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);
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}
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static const struct clk_ops slow_rc_osc_ops = {
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.prepare = clk_slow_rc_osc_prepare,
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.unprepare = clk_slow_rc_osc_unprepare,
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.is_prepared = clk_slow_rc_osc_is_prepared,
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.recalc_rate = clk_slow_rc_osc_recalc_rate,
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.recalc_accuracy = clk_slow_rc_osc_recalc_accuracy,
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};
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static struct clk_hw * __init
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at91_clk_register_slow_rc_osc(void __iomem *sckcr,
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const char *name,
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unsigned long frequency,
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unsigned long accuracy,
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unsigned long startup)
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{
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struct clk_slow_rc_osc *osc;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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if (!sckcr || !name)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &slow_rc_osc_ops;
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init.parent_names = NULL;
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init.num_parents = 0;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->sckcr = sckcr;
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osc->frequency = frequency;
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osc->accuracy = accuracy;
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osc->startup_usec = startup;
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hw = &osc->hw;
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ret = clk_hw_register(NULL, &osc->hw);
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if (ret) {
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kfree(osc);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void __init
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of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr)
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{
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struct clk_hw *hw;
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u32 frequency = 0;
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u32 accuracy = 0;
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u32 startup = 0;
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const char *name = np->name;
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of_property_read_string(np, "clock-output-names", &name);
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of_property_read_u32(np, "clock-frequency", &frequency);
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of_property_read_u32(np, "clock-accuracy", &accuracy);
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of_property_read_u32(np, "atmel,startup-time-usec", &startup);
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hw = at91_clk_register_slow_rc_osc(sckcr, name, frequency, accuracy,
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startup);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
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void __iomem *sckcr = slowck->sckcr;
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u32 tmp;
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if (index > 1)
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return -EINVAL;
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tmp = readl(sckcr);
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if ((!index && !(tmp & AT91_SCKC_OSCSEL)) ||
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(index && (tmp & AT91_SCKC_OSCSEL)))
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return 0;
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if (index)
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tmp |= AT91_SCKC_OSCSEL;
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else
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tmp &= ~AT91_SCKC_OSCSEL;
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writel(tmp, sckcr);
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usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
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return 0;
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}
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static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
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{
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struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
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return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);
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}
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static const struct clk_ops sam9x5_slow_ops = {
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.set_parent = clk_sam9x5_slow_set_parent,
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.get_parent = clk_sam9x5_slow_get_parent,
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};
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static struct clk_hw * __init
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at91_clk_register_sam9x5_slow(void __iomem *sckcr,
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const char *name,
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const char **parent_names,
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int num_parents)
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{
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struct clk_sam9x5_slow *slowck;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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if (!sckcr || !name || !parent_names || !num_parents)
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return ERR_PTR(-EINVAL);
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slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
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if (!slowck)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &sam9x5_slow_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = 0;
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slowck->hw.init = &init;
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slowck->sckcr = sckcr;
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slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);
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hw = &slowck->hw;
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ret = clk_hw_register(NULL, &slowck->hw);
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if (ret) {
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kfree(slowck);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void __init
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of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr)
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{
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struct clk_hw *hw;
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const char *parent_names[2];
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unsigned int num_parents;
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const char *name = np->name;
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num_parents = of_clk_get_parent_count(np);
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if (num_parents == 0 || num_parents > 2)
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return;
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of_clk_parent_fill(np, parent_names, num_parents);
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of_property_read_string(np, "clock-output-names", &name);
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hw = at91_clk_register_sam9x5_slow(sckcr, name, parent_names,
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num_parents);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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static const struct of_device_id sckc_clk_ids[] __initconst = {
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/* Slow clock */
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{
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.compatible = "atmel,at91sam9x5-clk-slow-osc",
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.data = of_at91sam9x5_clk_slow_osc_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-slow-rc-osc",
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.data = of_at91sam9x5_clk_slow_rc_osc_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-slow",
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.data = of_at91sam9x5_clk_slow_setup,
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},
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{ /*sentinel*/ }
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};
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static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
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{
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struct device_node *childnp;
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void (*clk_setup)(struct device_node *, void __iomem *);
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const struct of_device_id *clk_id;
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void __iomem *regbase = of_iomap(np, 0);
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if (!regbase)
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return;
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for_each_child_of_node(np, childnp) {
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clk_id = of_match_node(sckc_clk_ids, childnp);
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if (!clk_id)
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continue;
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clk_setup = clk_id->data;
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clk_setup(childnp, regbase);
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}
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}
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CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
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of_at91sam9x5_sckc_setup);
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static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
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{
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struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
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if (osc->prepared)
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return 0;
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/*
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* Assume that if it has already been selected (for example by the
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* bootloader), enough time has aready passed.
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*/
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if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) {
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osc->prepared = true;
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return 0;
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}
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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osc->prepared = true;
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return 0;
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}
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static int clk_sama5d4_slow_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
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return osc->prepared;
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}
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static const struct clk_ops sama5d4_slow_osc_ops = {
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.prepare = clk_sama5d4_slow_osc_prepare,
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.is_prepared = clk_sama5d4_slow_osc_is_prepared,
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};
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static void __init of_sama5d4_sckc_setup(struct device_node *np)
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{
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void __iomem *regbase = of_iomap(np, 0);
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struct clk_hw *hw;
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struct clk_sama5d4_slow_osc *osc;
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struct clk_init_data init;
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const char *xtal_name;
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const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
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bool bypass;
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int ret;
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if (!regbase)
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return;
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hw = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
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NULL, 0, 32768,
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250000000);
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if (IS_ERR(hw))
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return;
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xtal_name = of_clk_get_parent_name(np, 0);
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return;
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init.name = parent_names[1];
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init.ops = &sama5d4_slow_osc_ops;
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init.parent_names = &xtal_name;
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init.num_parents = 1;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->sckcr = regbase;
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osc->startup_usec = 1200000;
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if (bypass)
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writel((readl(regbase) | AT91_SCKC_OSC32BYP), regbase);
|
|
|
|
hw = &osc->hw;
|
|
ret = clk_hw_register(NULL, &osc->hw);
|
|
if (ret) {
|
|
kfree(osc);
|
|
return;
|
|
}
|
|
|
|
hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2);
|
|
if (IS_ERR(hw))
|
|
return;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
}
|
|
CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",
|
|
of_sama5d4_sckc_setup);
|