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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details [based] [from] [clk] [highbank] [c] you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 355 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154041.837383322@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Zynq power management
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*
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* Copyright (C) 2012 - 2014 Xilinx
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*
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* Sören Brinkmann <soren.brinkmann@xilinx.com>
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*/
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include "common.h"
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/* register offsets */
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#define DDRC_CTRL_REG1_OFFS 0x60
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#define DDRC_DRAM_PARAM_REG3_OFFS 0x20
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/* bitfields */
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#define DDRC_CLOCKSTOP_MASK BIT(23)
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#define DDRC_SELFREFRESH_MASK BIT(12)
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static void __iomem *ddrc_base;
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/**
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* zynq_pm_ioremap() - Create IO mappings
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* @comp: DT compatible string
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* Return: Pointer to the mapped memory or NULL.
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*
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* Remap the memory region for a compatible DT node.
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*/
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static void __iomem *zynq_pm_ioremap(const char *comp)
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{
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struct device_node *np;
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void __iomem *base = NULL;
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np = of_find_compatible_node(NULL, NULL, comp);
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if (np) {
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base = of_iomap(np, 0);
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of_node_put(np);
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} else {
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pr_warn("%s: no compatible node found for '%s'\n", __func__,
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comp);
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}
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return base;
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}
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/**
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* zynq_pm_late_init() - Power management init
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*
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* Initialization of power management related features and infrastructure.
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*/
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void __init zynq_pm_late_init(void)
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{
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u32 reg;
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ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05");
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if (!ddrc_base) {
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pr_warn("%s: Unable to map DDRC IO memory.\n", __func__);
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} else {
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/*
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* Enable DDRC clock stop feature. The HW takes care of
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* entering/exiting the correct mode depending
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* on activity state.
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*/
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reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
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reg |= DDRC_CLOCKSTOP_MASK;
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writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
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}
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}
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