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Example memory map (from HP sx1000 with VGA enabled):
0x00000 - 0x9FFFF supports only WB (cacheable) access
0xA0000 - 0xBFFFF supports only UC (uncacheable) access
0xC0000 - 0xFFFFF supports only WB (cacheable) access
pci_read_rom() indirectly uses ioremap(0xC0000) to read the shadow VGA option
ROM. ioremap() used to default to a 16MB or 64MB UC kernel identity mapping,
which would cause an MCA when reading 0xC0000 since only WB is supported there.
X uses reads the option ROM to initialize devices. A smaller test case is:
# echo 1 > /sys/bus/pci/devices/0000:aa:03.0/rom
# cp /sys/bus/pci/devices/0000:aa:03.0/rom x
To avoid this, we can use the same ioremap_page_range() strategy that most
architectures use for all ioremaps. These page table mappings come out of the
vmalloc area. On ia64, these are in region 5 (0xA... addresses) and typically
use 16KB or 64KB mappings instead of 16MB or 64MB mappings. The smaller
mappings give more flexibility to use the correct attributes.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* (c) Copyright 2006, 2007 Hewlett-Packard Development Company, L.P.
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* Bjorn Helgaas <bjorn.helgaas@hp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/compiler.h>
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#include <linux/module.h>
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#include <linux/efi.h>
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#include <linux/io.h>
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#include <linux/vmalloc.h>
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#include <asm/io.h>
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#include <asm/meminit.h>
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static inline void __iomem *
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__ioremap (unsigned long phys_addr)
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{
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return (void __iomem *) (__IA64_UNCACHED_OFFSET | phys_addr);
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}
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void __iomem *
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ioremap (unsigned long phys_addr, unsigned long size)
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{
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void __iomem *addr;
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struct vm_struct *area;
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unsigned long offset;
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pgprot_t prot;
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u64 attr;
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unsigned long gran_base, gran_size;
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unsigned long page_base;
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/*
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* For things in kern_memmap, we must use the same attribute
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* as the rest of the kernel. For more details, see
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* Documentation/ia64/aliasing.txt.
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*/
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attr = kern_mem_attribute(phys_addr, size);
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if (attr & EFI_MEMORY_WB)
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return (void __iomem *) phys_to_virt(phys_addr);
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else if (attr & EFI_MEMORY_UC)
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return __ioremap(phys_addr);
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/*
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* Some chipsets don't support UC access to memory. If
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* WB is supported for the whole granule, we prefer that.
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*/
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gran_base = GRANULEROUNDDOWN(phys_addr);
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gran_size = GRANULEROUNDUP(phys_addr + size) - gran_base;
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if (efi_mem_attribute(gran_base, gran_size) & EFI_MEMORY_WB)
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return (void __iomem *) phys_to_virt(phys_addr);
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/*
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* WB is not supported for the whole granule, so we can't use
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* the region 7 identity mapping. If we can safely cover the
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* area with kernel page table mappings, we can use those
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* instead.
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*/
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page_base = phys_addr & PAGE_MASK;
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size = PAGE_ALIGN(phys_addr + size) - page_base;
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if (efi_mem_attribute(page_base, size) & EFI_MEMORY_WB) {
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prot = PAGE_KERNEL;
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/*
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* Mappings have to be page-aligned
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*/
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offset = phys_addr & ~PAGE_MASK;
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phys_addr &= PAGE_MASK;
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/*
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* Ok, go for it..
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*/
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area = get_vm_area(size, VM_IOREMAP);
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if (!area)
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return NULL;
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area->phys_addr = phys_addr;
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addr = (void __iomem *) area->addr;
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if (ioremap_page_range((unsigned long) addr,
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(unsigned long) addr + size, phys_addr, prot)) {
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vunmap((void __force *) addr);
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return NULL;
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}
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return (void __iomem *) (offset + (char __iomem *)addr);
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}
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return __ioremap(phys_addr);
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}
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EXPORT_SYMBOL(ioremap);
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void __iomem *
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ioremap_nocache (unsigned long phys_addr, unsigned long size)
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{
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if (kern_mem_attribute(phys_addr, size) & EFI_MEMORY_WB)
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return NULL;
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return __ioremap(phys_addr);
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}
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EXPORT_SYMBOL(ioremap_nocache);
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void
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iounmap (volatile void __iomem *addr)
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{
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if (REGION_NUMBER(addr) == RGN_GATE)
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vunmap((void *) ((unsigned long) addr & PAGE_MASK));
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}
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EXPORT_SYMBOL(iounmap);
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