Cyril Bur 5d176f751e powerpc: tm: Enable transactional memory (TM) lazily for userspace ... Currently the MSR TM bit is always set if the hardware is TM capable. This adds extra overhead as it means the TM SPRS (TFHAR, TEXASR and TFAIR) must be swapped for each process regardless of if they use TM. For processes that don't use TM the TM MSR bit can be turned off allowing the kernel to avoid the expensive swap of the TM registers. A TM unavailable exception will occur if a thread does use TM and the kernel will enable MSR_TM and leave it so for some time afterwards. Signed-off-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>		2016-10-04 20:33:17 +11:00
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asm	powerpc: tm: Enable transactional memory (TM) lazily for userspace	2016-10-04 20:33:17 +11:00
uapi/asm	powerpc/ptrace: Enable support for Performance Monitor registers	2016-08-01 11:15:24 +10:00