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5cea24c589
Pull second set of ARM updates from Russell King: "This is the second set of ARM updates for this merge window. Contained within are changes to allow the kernel to boot in hypervisor mode on CPUs supporting virtualization, and cache flushing support to the point of inner sharable unification, which are used by the suspend/resume code to avoid having to do a full cache flush. Also included is one fix for VFP code identified by Michael Olbrich." * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: ARM: vfp: fix saving d16-d31 vfp registers on v6+ kernels ARM: 7549/1: HYP: fix boot on some ARM1136 cores ARM: 7542/1: mm: fix cache LoUIS API for xscale and feroceon ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API ARM: kernel: update cpu_suspend code to use cache LoUIS operations ARM: mm: rename jump labels in v7_flush_dcache_all function ARM: mm: implement LoUIS API for cache maintenance ops ARM: virt: arch_timers: enable access to physical timers ARM: virt: Add CONFIG_ARM_VIRT_EXT option ARM: virt: Add boot-time diagnostics ARM: virt: Update documentation for hyp mode entry support ARM: zImage/virt: hyp mode entry support for the zImage loader ARM: virt: allow the kernel to be entered in HYP mode ARM: opcodes: add __ERET/__MSR_ELR_HYP instruction encoding
269 lines
6.6 KiB
C
269 lines
6.6 KiB
C
/*
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* arch/arm/include/asm/ptrace.h
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*
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* Copyright (C) 1996-2003 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_PTRACE_H
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#define __ASM_ARM_PTRACE_H
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#include <asm/hwcap.h>
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#define PTRACE_GETREGS 12
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#define PTRACE_SETREGS 13
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#define PTRACE_GETFPREGS 14
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#define PTRACE_SETFPREGS 15
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/* PTRACE_ATTACH is 16 */
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/* PTRACE_DETACH is 17 */
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#define PTRACE_GETWMMXREGS 18
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#define PTRACE_SETWMMXREGS 19
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/* 20 is unused */
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#define PTRACE_OLDSETOPTIONS 21
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#define PTRACE_GET_THREAD_AREA 22
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#define PTRACE_SET_SYSCALL 23
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/* PTRACE_SYSCALL is 24 */
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#define PTRACE_GETCRUNCHREGS 25
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#define PTRACE_SETCRUNCHREGS 26
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#define PTRACE_GETVFPREGS 27
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#define PTRACE_SETVFPREGS 28
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#define PTRACE_GETHBPREGS 29
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#define PTRACE_SETHBPREGS 30
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/*
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* PSR bits
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*/
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#define USR26_MODE 0x00000000
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#define FIQ26_MODE 0x00000001
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#define IRQ26_MODE 0x00000002
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#define SVC26_MODE 0x00000003
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#define USR_MODE 0x00000010
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#define FIQ_MODE 0x00000011
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#define IRQ_MODE 0x00000012
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#define SVC_MODE 0x00000013
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#define ABT_MODE 0x00000017
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#define HYP_MODE 0x0000001a
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#define UND_MODE 0x0000001b
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#define SYSTEM_MODE 0x0000001f
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#define MODE32_BIT 0x00000010
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#define MODE_MASK 0x0000001f
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#define PSR_T_BIT 0x00000020
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#define PSR_F_BIT 0x00000040
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#define PSR_I_BIT 0x00000080
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#define PSR_A_BIT 0x00000100
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#define PSR_E_BIT 0x00000200
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#define PSR_J_BIT 0x01000000
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#define PSR_Q_BIT 0x08000000
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#define PSR_V_BIT 0x10000000
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#define PSR_C_BIT 0x20000000
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#define PSR_Z_BIT 0x40000000
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#define PSR_N_BIT 0x80000000
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/*
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* Groups of PSR bits
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*/
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#define PSR_f 0xff000000 /* Flags */
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#define PSR_s 0x00ff0000 /* Status */
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#define PSR_x 0x0000ff00 /* Extension */
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#define PSR_c 0x000000ff /* Control */
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/*
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* ARMv7 groups of PSR bits
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*/
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#define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */
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#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
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#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
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#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
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/*
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* Default endianness state
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*/
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#define PSR_ENDSTATE PSR_E_BIT
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#else
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#define PSR_ENDSTATE 0
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#endif
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/*
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* These are 'magic' values for PTRACE_PEEKUSR that return info about where a
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* process is located in memory.
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*/
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#define PT_TEXT_ADDR 0x10000
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#define PT_DATA_ADDR 0x10004
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#define PT_TEXT_END_ADDR 0x10008
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#ifndef __ASSEMBLY__
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/*
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* This struct defines the way the registers are stored on the
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* stack during a system call. Note that sizeof(struct pt_regs)
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* has to be a multiple of 8.
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*/
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#ifndef __KERNEL__
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struct pt_regs {
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long uregs[18];
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};
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#else /* __KERNEL__ */
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struct pt_regs {
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unsigned long uregs[18];
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};
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#endif /* __KERNEL__ */
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#define ARM_cpsr uregs[16]
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#define ARM_pc uregs[15]
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#define ARM_lr uregs[14]
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#define ARM_sp uregs[13]
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#define ARM_ip uregs[12]
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#define ARM_fp uregs[11]
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#define ARM_r10 uregs[10]
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#define ARM_r9 uregs[9]
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#define ARM_r8 uregs[8]
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#define ARM_r7 uregs[7]
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#define ARM_r6 uregs[6]
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#define ARM_r5 uregs[5]
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#define ARM_r4 uregs[4]
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#define ARM_r3 uregs[3]
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#define ARM_r2 uregs[2]
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#define ARM_r1 uregs[1]
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#define ARM_r0 uregs[0]
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#define ARM_ORIG_r0 uregs[17]
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/*
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* The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
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* and core dumps.
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*/
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#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ )
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#ifdef __KERNEL__
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#define user_mode(regs) \
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(((regs)->ARM_cpsr & 0xf) == 0)
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#ifdef CONFIG_ARM_THUMB
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#define thumb_mode(regs) \
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(((regs)->ARM_cpsr & PSR_T_BIT))
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#else
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#define thumb_mode(regs) (0)
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#endif
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#define isa_mode(regs) \
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((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
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(((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
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#define processor_mode(regs) \
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((regs)->ARM_cpsr & MODE_MASK)
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#define interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & PSR_I_BIT))
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#define fast_interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & PSR_F_BIT))
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/* Are the current registers suitable for user mode?
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* (used to maintain security in signal handlers)
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*/
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static inline int valid_user_regs(struct pt_regs *regs)
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{
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unsigned long mode = regs->ARM_cpsr & MODE_MASK;
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/*
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* Always clear the F (FIQ) and A (delayed abort) bits
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*/
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regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
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if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
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if (mode == USR_MODE)
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return 1;
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if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
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return 1;
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}
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/*
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* Force CPSR to something logical...
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*/
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regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
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if (!(elf_hwcap & HWCAP_26BIT))
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regs->ARM_cpsr |= USR_MODE;
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return 0;
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}
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static inline long regs_return_value(struct pt_regs *regs)
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{
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return regs->ARM_r0;
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}
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#define instruction_pointer(regs) (regs)->ARM_pc
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#ifdef CONFIG_SMP
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extern unsigned long profile_pc(struct pt_regs *regs);
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#else
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#define profile_pc(regs) instruction_pointer(regs)
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#endif
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#define predicate(x) ((x) & 0xf0000000)
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#define PREDICATE_ALWAYS 0xe0000000
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/*
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* True if instr is a 32-bit thumb instruction. This works if instr
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* is the first or only half-word of a thumb instruction. It also works
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* when instr holds all 32-bits of a wide thumb instruction if stored
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* in the form (first_half<<16)|(second_half)
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*/
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#define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800)
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/*
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* kprobe-based event tracer support
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*/
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#include <linux/stddef.h>
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#include <linux/types.h>
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#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
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extern int regs_query_register_offset(const char *name);
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extern const char *regs_query_register_name(unsigned int offset);
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extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
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extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
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unsigned int n);
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/**
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* regs_get_register() - get register value from its offset
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* @regs: pt_regs from which register value is gotten
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* @offset: offset number of the register.
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*
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* regs_get_register returns the value of a register whose offset from @regs.
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* The @offset is the offset of the register in struct pt_regs.
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* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
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*/
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static inline unsigned long regs_get_register(struct pt_regs *regs,
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unsigned int offset)
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{
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if (unlikely(offset > MAX_REG_OFFSET))
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return 0;
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return *(unsigned long *)((unsigned long)regs + offset);
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}
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/* Valid only for Kernel mode traps. */
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static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
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{
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return regs->ARM_sp;
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}
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static inline unsigned long user_stack_pointer(struct pt_regs *regs)
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{
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return regs->ARM_sp;
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}
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#define current_pt_regs(void) ({ \
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register unsigned long sp asm ("sp"); \
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(struct pt_regs *)((sp | (THREAD_SIZE - 1)) - 7) - 1; \
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})
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif
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