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In ISOC transfers, when free_slot points to the last TRB (i.e. Link TRB), and all queued requests meet Missed Interval Isoc error, busy_slot points to trb0. busy_slot->trb0 trb1 ... free_slot->trb31(Link TRB) After end transfer and receiving the XferNotReady event, trb_left is caculated as 1 which is wrong, and no TRB will be primed to the endpoint. The root cause is free_slot is not increased the same way as busy_slot. When busy_slot is increased by one, it checks if points to a link TRB after increasement, but free_slot checks it before increasement. free_slot should behave the same as busy_slot to make the trb_left caculation correct. Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Zhuang Jin Can <jin.can.zhuang@intel.com> Signed-off-by: Jiebing Li <jiebing.li@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com> |
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| .. | ||
| core.c | ||
| core.h | ||
| debug.h | ||
| debugfs.c | ||
| dwc3-exynos.c | ||
| dwc3-keystone.c | ||
| dwc3-omap.c | ||
| dwc3-pci.c | ||
| ep0.c | ||
| gadget.c | ||
| gadget.h | ||
| host.c | ||
| io.h | ||
| Kconfig | ||
| Makefile | ||
| platform_data.h | ||