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The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where interrupts are routed from the networking hardware to the XSL using the MSIX table, and from there will be transformed back into an MSIX interrupt using the cxl style interrupts (i.e. using IVTE entries and ranges to map a PE and AFU interrupt number to an MSIX address). We want to hide the implementation details of cxl interrupts as much as possible. To this end, we use a special version of the MSI setup & teardown routines in the PHB while in cxl mode to allocate the cxl interrupts and configure the IVTE entries in the process element. This function does not configure the MSIX table - the CX4 card uses a custom format in that table and it would not be appropriate to fill that out in generic code. The rest of the functionality is similar to the "Full MSI-X mode" described in the CAIA, and this could be easily extended to support other adapters that use that mode in the future. The interrupts will be associated with the default context. If the maximum number of interrupts per context has been limited (e.g. by the mlx5 driver), it will automatically allocate additional kernel contexts to associate extra interrupts as required. These contexts will be started using the same WED that was used to start the default context. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
63 lines
1.8 KiB
C
63 lines
1.8 KiB
C
/*
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* Copyright 2014 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _MISC_CXL_BASE_H
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#define _MISC_CXL_BASE_H
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#include <misc/cxl.h>
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#ifdef CONFIG_CXL_BASE
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#define CXL_IRQ_RANGES 4
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struct cxl_irq_ranges {
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irq_hw_number_t offset[CXL_IRQ_RANGES];
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irq_hw_number_t range[CXL_IRQ_RANGES];
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};
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extern atomic_t cxl_use_count;
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static inline bool cxl_ctx_in_use(void)
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{
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return (atomic_read(&cxl_use_count) != 0);
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}
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static inline void cxl_ctx_get(void)
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{
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atomic_inc(&cxl_use_count);
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}
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static inline void cxl_ctx_put(void)
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{
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atomic_dec(&cxl_use_count);
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}
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struct cxl_afu *cxl_afu_get(struct cxl_afu *afu);
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void cxl_afu_put(struct cxl_afu *afu);
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void cxl_slbia(struct mm_struct *mm);
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bool cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
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void cxl_pci_disable_device(struct pci_dev *dev);
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int cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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void cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
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#else /* CONFIG_CXL_BASE */
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static inline bool cxl_ctx_in_use(void) { return false; }
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static inline struct cxl_afu *cxl_afu_get(struct cxl_afu *afu) { return NULL; }
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static inline void cxl_afu_put(struct cxl_afu *afu) {}
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static inline void cxl_slbia(struct mm_struct *mm) {}
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static inline bool cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu) { return false; }
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static inline void cxl_pci_disable_device(struct pci_dev *dev) {}
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static inline int cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) { return -ENODEV; }
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static inline void cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev) {}
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#endif /* CONFIG_CXL_BASE */
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#endif
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