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0172dc6562
Signed-off-by: Jitendra Bhivare <jitendra.bhivare@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
211 lines
5.3 KiB
C
211 lines
5.3 KiB
C
/*
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* Copyright 2017 Broadcom. All Rights Reserved.
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* The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@broadcom.com
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*
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*/
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#ifndef BEISCSI_H
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#define BEISCSI_H
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#include <linux/pci.h>
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#include <linux/if_vlan.h>
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#include <linux/irq_poll.h>
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#define FW_VER_LEN 32
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#define MCC_Q_LEN 128
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#define MCC_CQ_LEN 256
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#define MAX_MCC_CMD 16
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/* BladeEngine Generation numbers */
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#define BE_GEN2 2
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#define BE_GEN3 3
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#define BE_GEN4 4
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struct be_dma_mem {
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void *va;
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dma_addr_t dma;
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u32 size;
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};
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struct be_queue_info {
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struct be_dma_mem dma_mem;
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u16 len;
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u16 entry_size; /* Size of an element in the queue */
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u16 id;
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u16 tail, head;
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bool created;
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u16 used; /* Number of valid elements in the queue */
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};
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static inline u32 MODULO(u16 val, u16 limit)
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{
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WARN_ON(limit & (limit - 1));
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return val & (limit - 1);
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}
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static inline void index_inc(u16 *index, u16 limit)
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{
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*index = MODULO((*index + 1), limit);
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}
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static inline void *queue_head_node(struct be_queue_info *q)
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{
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return q->dma_mem.va + q->head * q->entry_size;
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}
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static inline void *queue_get_wrb(struct be_queue_info *q, unsigned int wrb_num)
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{
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return q->dma_mem.va + wrb_num * q->entry_size;
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}
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static inline void *queue_tail_node(struct be_queue_info *q)
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{
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return q->dma_mem.va + q->tail * q->entry_size;
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}
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static inline void queue_head_inc(struct be_queue_info *q)
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{
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index_inc(&q->head, q->len);
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}
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static inline void queue_tail_inc(struct be_queue_info *q)
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{
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index_inc(&q->tail, q->len);
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}
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/*ISCSI */
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struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
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unsigned long jiffies;
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u32 eq_prev; /* Used to calculate eqe */
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u32 prev_eqd;
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#define BEISCSI_EQ_DELAY_MIN 0
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#define BEISCSI_EQ_DELAY_DEF 32
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#define BEISCSI_EQ_DELAY_MAX 128
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};
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struct be_eq_obj {
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u32 cq_count;
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struct be_queue_info q;
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struct beiscsi_hba *phba;
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struct be_queue_info *cq;
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struct work_struct mcc_work; /* Work Item */
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struct irq_poll iopoll;
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};
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struct be_mcc_obj {
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struct be_queue_info q;
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struct be_queue_info cq;
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};
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struct beiscsi_mcc_tag_state {
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unsigned long tag_state;
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#define MCC_TAG_STATE_RUNNING 0
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#define MCC_TAG_STATE_TIMEOUT 1
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#define MCC_TAG_STATE_ASYNC 2
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#define MCC_TAG_STATE_IGNORE 3
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void (*cbfn)(struct beiscsi_hba *, unsigned int);
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struct be_dma_mem tag_mem_state;
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};
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struct be_ctrl_info {
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u8 __iomem *csr;
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u8 __iomem *db; /* Door Bell */
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u8 __iomem *pcicfg; /* PCI config space */
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struct pci_dev *pdev;
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/* Mbox used for cmd request/response */
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struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
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struct be_dma_mem mbox_mem;
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/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
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* is stored for freeing purpose */
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struct be_dma_mem mbox_mem_alloced;
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/* MCC Rings */
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struct be_mcc_obj mcc_obj;
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spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
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wait_queue_head_t mcc_wait[MAX_MCC_CMD + 1];
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unsigned int mcc_tag[MAX_MCC_CMD];
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unsigned int mcc_tag_status[MAX_MCC_CMD + 1];
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unsigned short mcc_alloc_index;
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unsigned short mcc_free_index;
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unsigned int mcc_tag_available;
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struct beiscsi_mcc_tag_state ptag_state[MAX_MCC_CMD + 1];
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};
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#include "be_cmds.h"
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/* WRB index mask for MCC_Q_LEN queue entries */
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#define MCC_Q_WRB_IDX_MASK CQE_STATUS_WRB_MASK
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#define MCC_Q_WRB_IDX_SHIFT CQE_STATUS_WRB_SHIFT
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/* TAG is from 1...MAX_MCC_CMD, MASK includes MAX_MCC_CMD */
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#define MCC_Q_CMD_TAG_MASK ((MAX_MCC_CMD << 1) - 1)
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#define PAGE_SHIFT_4K 12
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#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
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/* Returns number of pages spanned by the data starting at the given addr */
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#define PAGES_4K_SPANNED(_address, size) \
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((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
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(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
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/* Returns bit offset within a DWORD of a bitfield */
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#define AMAP_BIT_OFFSET(_struct, field) \
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(((size_t)&(((_struct *)0)->field))%32)
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/* Returns the bit mask of the field that is NOT shifted into location. */
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static inline u32 amap_mask(u32 bitsize)
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{
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return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
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}
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static inline void amap_set(void *ptr, u32 dw_offset, u32 mask,
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u32 offset, u32 value)
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{
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u32 *dw = (u32 *) ptr + dw_offset;
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*dw &= ~(mask << offset);
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*dw |= (mask & value) << offset;
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}
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#define AMAP_SET_BITS(_struct, field, ptr, val) \
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amap_set(ptr, \
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offsetof(_struct, field)/32, \
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amap_mask(sizeof(((_struct *)0)->field)), \
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AMAP_BIT_OFFSET(_struct, field), \
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val)
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static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
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{
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u32 *dw = ptr;
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return mask & (*(dw + dw_offset) >> offset);
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}
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#define AMAP_GET_BITS(_struct, field, ptr) \
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amap_get(ptr, \
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offsetof(_struct, field)/32, \
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amap_mask(sizeof(((_struct *)0)->field)), \
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AMAP_BIT_OFFSET(_struct, field))
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#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
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#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
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static inline void swap_dws(void *wrb, int len)
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{
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#ifdef __BIG_ENDIAN
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u32 *dw = wrb;
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WARN_ON(len % 4);
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do {
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*dw = cpu_to_le32(*dw);
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dw++;
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len -= 4;
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} while (len);
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#endif /* __BIG_ENDIAN */
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}
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#endif /* BEISCSI_H */
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