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20342e3f64
The x86 SHA-1 module contains four implementations: SSSE3, AVX, AVX2,
and SHA-NI. Commit 1c43c0f1f8 ("crypto: x86/sha - load modules based
on CPU features") made the module be autoloaded when SSSE3, AVX, or AVX2
is detected. The omission of SHA-NI appears to be an oversight, perhaps
because of the outdated file-level comment. This patch fixes this,
though in practice this makes no difference because SSSE3 is a subset of
the other three features anyway. Indeed, sha1_ni_transform() executes
SSSE3 instructions such as pshufb.
Reviewed-by: Roxana Nicolescu <roxana.nicolescu@canonical.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
366 lines
8.6 KiB
C
366 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Cryptographic API.
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*
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* Glue code for the SHA1 Secure Hash Algorithm assembler implementations
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* using SSSE3, AVX, AVX2, and SHA-NI instructions.
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*
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* This file is based on sha1_generic.c
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*
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* Copyright (c) Alan Smithee.
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* Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
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* Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
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* Copyright (c) Mathias Krause <minipli@googlemail.com>
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* Copyright (c) Chandramouli Narayanan <mouli@linux.intel.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <crypto/internal/hash.h>
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#include <crypto/internal/simd.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/types.h>
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#include <crypto/sha1.h>
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#include <crypto/sha1_base.h>
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#include <asm/cpu_device_id.h>
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#include <asm/simd.h>
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static const struct x86_cpu_id module_cpu_ids[] = {
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#ifdef CONFIG_AS_SHA1_NI
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X86_MATCH_FEATURE(X86_FEATURE_SHA_NI, NULL),
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#endif
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X86_MATCH_FEATURE(X86_FEATURE_AVX2, NULL),
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X86_MATCH_FEATURE(X86_FEATURE_AVX, NULL),
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X86_MATCH_FEATURE(X86_FEATURE_SSSE3, NULL),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, module_cpu_ids);
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static int sha1_update(struct shash_desc *desc, const u8 *data,
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unsigned int len, sha1_block_fn *sha1_xform)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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if (!crypto_simd_usable() ||
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(sctx->count % SHA1_BLOCK_SIZE) + len < SHA1_BLOCK_SIZE)
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return crypto_sha1_update(desc, data, len);
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/*
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* Make sure struct sha1_state begins directly with the SHA1
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* 160-bit internal state, as this is what the asm functions expect.
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*/
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BUILD_BUG_ON(offsetof(struct sha1_state, state) != 0);
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kernel_fpu_begin();
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sha1_base_do_update(desc, data, len, sha1_xform);
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kernel_fpu_end();
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return 0;
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}
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static int sha1_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out, sha1_block_fn *sha1_xform)
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{
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if (!crypto_simd_usable())
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return crypto_sha1_finup(desc, data, len, out);
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kernel_fpu_begin();
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if (len)
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sha1_base_do_update(desc, data, len, sha1_xform);
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sha1_base_do_finalize(desc, sha1_xform);
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kernel_fpu_end();
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return sha1_base_finish(desc, out);
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}
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asmlinkage void sha1_transform_ssse3(struct sha1_state *state,
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const u8 *data, int blocks);
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static int sha1_ssse3_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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return sha1_update(desc, data, len, sha1_transform_ssse3);
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}
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static int sha1_ssse3_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha1_finup(desc, data, len, out, sha1_transform_ssse3);
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}
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/* Add padding and return the message digest. */
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static int sha1_ssse3_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_ssse3_finup(desc, NULL, 0, out);
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}
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static struct shash_alg sha1_ssse3_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_ssse3_update,
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.final = sha1_ssse3_final,
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.finup = sha1_ssse3_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-ssse3",
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.cra_priority = 150,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static int register_sha1_ssse3(void)
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{
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if (boot_cpu_has(X86_FEATURE_SSSE3))
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return crypto_register_shash(&sha1_ssse3_alg);
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return 0;
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}
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static void unregister_sha1_ssse3(void)
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{
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if (boot_cpu_has(X86_FEATURE_SSSE3))
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crypto_unregister_shash(&sha1_ssse3_alg);
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}
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asmlinkage void sha1_transform_avx(struct sha1_state *state,
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const u8 *data, int blocks);
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static int sha1_avx_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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return sha1_update(desc, data, len, sha1_transform_avx);
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}
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static int sha1_avx_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha1_finup(desc, data, len, out, sha1_transform_avx);
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}
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static int sha1_avx_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_avx_finup(desc, NULL, 0, out);
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}
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static struct shash_alg sha1_avx_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_avx_update,
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.final = sha1_avx_final,
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.finup = sha1_avx_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-avx",
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.cra_priority = 160,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static bool avx_usable(void)
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{
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if (!cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL)) {
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if (boot_cpu_has(X86_FEATURE_AVX))
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pr_info("AVX detected but unusable.\n");
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return false;
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}
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return true;
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}
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static int register_sha1_avx(void)
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{
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if (avx_usable())
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return crypto_register_shash(&sha1_avx_alg);
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return 0;
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}
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static void unregister_sha1_avx(void)
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{
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if (avx_usable())
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crypto_unregister_shash(&sha1_avx_alg);
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}
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#define SHA1_AVX2_BLOCK_OPTSIZE 4 /* optimal 4*64 bytes of SHA1 blocks */
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asmlinkage void sha1_transform_avx2(struct sha1_state *state,
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const u8 *data, int blocks);
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static bool avx2_usable(void)
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{
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if (avx_usable() && boot_cpu_has(X86_FEATURE_AVX2)
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&& boot_cpu_has(X86_FEATURE_BMI1)
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&& boot_cpu_has(X86_FEATURE_BMI2))
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return true;
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return false;
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}
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static void sha1_apply_transform_avx2(struct sha1_state *state,
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const u8 *data, int blocks)
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{
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/* Select the optimal transform based on data block size */
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if (blocks >= SHA1_AVX2_BLOCK_OPTSIZE)
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sha1_transform_avx2(state, data, blocks);
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else
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sha1_transform_avx(state, data, blocks);
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}
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static int sha1_avx2_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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return sha1_update(desc, data, len, sha1_apply_transform_avx2);
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}
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static int sha1_avx2_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha1_finup(desc, data, len, out, sha1_apply_transform_avx2);
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}
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static int sha1_avx2_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_avx2_finup(desc, NULL, 0, out);
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}
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static struct shash_alg sha1_avx2_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_avx2_update,
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.final = sha1_avx2_final,
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.finup = sha1_avx2_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-avx2",
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.cra_priority = 170,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static int register_sha1_avx2(void)
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{
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if (avx2_usable())
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return crypto_register_shash(&sha1_avx2_alg);
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return 0;
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}
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static void unregister_sha1_avx2(void)
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{
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if (avx2_usable())
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crypto_unregister_shash(&sha1_avx2_alg);
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}
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#ifdef CONFIG_AS_SHA1_NI
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asmlinkage void sha1_ni_transform(struct sha1_state *digest, const u8 *data,
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int rounds);
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static int sha1_ni_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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return sha1_update(desc, data, len, sha1_ni_transform);
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}
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static int sha1_ni_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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return sha1_finup(desc, data, len, out, sha1_ni_transform);
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}
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static int sha1_ni_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_ni_finup(desc, NULL, 0, out);
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}
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static struct shash_alg sha1_ni_alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_ni_update,
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.final = sha1_ni_final,
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.finup = sha1_ni_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-ni",
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.cra_priority = 250,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static int register_sha1_ni(void)
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{
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if (boot_cpu_has(X86_FEATURE_SHA_NI))
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return crypto_register_shash(&sha1_ni_alg);
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return 0;
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}
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static void unregister_sha1_ni(void)
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{
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if (boot_cpu_has(X86_FEATURE_SHA_NI))
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crypto_unregister_shash(&sha1_ni_alg);
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}
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#else
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static inline int register_sha1_ni(void) { return 0; }
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static inline void unregister_sha1_ni(void) { }
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#endif
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static int __init sha1_ssse3_mod_init(void)
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{
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if (!x86_match_cpu(module_cpu_ids))
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return -ENODEV;
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if (register_sha1_ssse3())
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goto fail;
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if (register_sha1_avx()) {
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unregister_sha1_ssse3();
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goto fail;
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}
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if (register_sha1_avx2()) {
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unregister_sha1_avx();
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unregister_sha1_ssse3();
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goto fail;
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}
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if (register_sha1_ni()) {
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unregister_sha1_avx2();
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unregister_sha1_avx();
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unregister_sha1_ssse3();
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goto fail;
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}
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return 0;
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fail:
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return -ENODEV;
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}
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static void __exit sha1_ssse3_mod_fini(void)
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{
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unregister_sha1_ni();
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unregister_sha1_avx2();
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unregister_sha1_avx();
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unregister_sha1_ssse3();
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}
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module_init(sha1_ssse3_mod_init);
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module_exit(sha1_ssse3_mod_fini);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, Supplemental SSE3 accelerated");
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MODULE_ALIAS_CRYPTO("sha1");
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MODULE_ALIAS_CRYPTO("sha1-ssse3");
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MODULE_ALIAS_CRYPTO("sha1-avx");
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MODULE_ALIAS_CRYPTO("sha1-avx2");
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#ifdef CONFIG_AS_SHA1_NI
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MODULE_ALIAS_CRYPTO("sha1-ni");
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#endif
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