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The AIU audio controller on the Meson8 and Meson8b SoC families is compatible with the one found in the later GXBB family. Add compatible strings for these two older SoC families so the driver can be loaded for them. Instead of using the I2S divider from the AIU_CLK_CTRL_MORE register we need to use the I2S divider from the AIU_CLK_CTRL register. This older register is less flexible because it only supports four divider settings (1, 2, 4, 8) compared to the AIU_CLK_CTRL_MORE register (which supports dividers in the range 0..64). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200220205711.77953-4-martin.blumenstingl@googlemail.com Signed-off-by: Mark Brown <broonie@kernel.org>
90 lines
2.2 KiB
C
90 lines
2.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef _MESON_AIU_H
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#define _MESON_AIU_H
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struct clk;
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struct clk_bulk_data;
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struct device;
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struct of_phandle_args;
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struct snd_soc_dai;
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struct snd_soc_dai_ops;
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enum aiu_clk_ids {
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PCLK = 0,
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AOCLK,
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MCLK,
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MIXER
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};
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struct aiu_interface {
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struct clk_bulk_data *clks;
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unsigned int clk_num;
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int irq;
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};
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struct aiu_platform_data {
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bool has_acodec;
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bool has_clk_ctrl_more_i2s_div;
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};
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struct aiu {
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struct clk *pclk;
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struct clk *spdif_mclk;
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struct aiu_interface i2s;
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struct aiu_interface spdif;
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const struct aiu_platform_data *platform;
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};
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#define AIU_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S20_LE | \
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SNDRV_PCM_FMTBIT_S24_LE)
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int aiu_of_xlate_dai_name(struct snd_soc_component *component,
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struct of_phandle_args *args,
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const char **dai_name,
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unsigned int component_id);
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int aiu_hdmi_ctrl_register_component(struct device *dev);
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int aiu_acodec_ctrl_register_component(struct device *dev);
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int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai);
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int aiu_fifo_spdif_dai_probe(struct snd_soc_dai *dai);
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extern const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops;
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extern const struct snd_soc_dai_ops aiu_fifo_spdif_dai_ops;
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extern const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops;
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extern const struct snd_soc_dai_ops aiu_encoder_spdif_dai_ops;
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#define AIU_IEC958_BPF 0x000
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#define AIU_958_MISC 0x010
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#define AIU_IEC958_DCU_FF_CTRL 0x01c
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#define AIU_958_CHSTAT_L0 0x020
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#define AIU_958_CHSTAT_L1 0x024
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#define AIU_958_CTRL 0x028
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#define AIU_I2S_SOURCE_DESC 0x034
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#define AIU_I2S_DAC_CFG 0x040
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#define AIU_I2S_SYNC 0x044
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#define AIU_I2S_MISC 0x048
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#define AIU_RST_SOFT 0x054
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#define AIU_CLK_CTRL 0x058
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#define AIU_CLK_CTRL_MORE 0x064
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#define AIU_CODEC_DAC_LRCLK_CTRL 0x0a0
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#define AIU_HDMI_CLK_DATA_CTRL 0x0a8
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#define AIU_ACODEC_CTRL 0x0b0
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#define AIU_958_CHSTAT_R0 0x0c0
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#define AIU_958_CHSTAT_R1 0x0c4
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#define AIU_MEM_I2S_START 0x180
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#define AIU_MEM_I2S_MASKS 0x18c
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#define AIU_MEM_I2S_CONTROL 0x190
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#define AIU_MEM_IEC958_START 0x194
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#define AIU_MEM_IEC958_CONTROL 0x1a4
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#define AIU_MEM_I2S_BUF_CNTL 0x1d8
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#define AIU_MEM_IEC958_BUF_CNTL 0x1fc
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#endif /* _MESON_AIU_H */
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