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e2c37d9083
The PPC476GTR SoC supports message signalled interrupts (MSI) by writing to special addresses within the High Speed Transfer Assist (HSTA) module. This patch adds support for PCI MSI with a new system device. The DMA window is also updated to allow access to the entire 42-bit address range to allow PCI devices write access to the HSTA module. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
216 lines
4.9 KiB
C
216 lines
4.9 KiB
C
/*
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* MSI support for PPC4xx SoCs using High Speed Transfer Assist (HSTA) for
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* generation of the interrupt.
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*
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* Copyright © 2013 Alistair Popple <alistair@popple.id.au> IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/semaphore.h>
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#include <asm/msi_bitmap.h>
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struct ppc4xx_hsta_msi {
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struct device *dev;
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/* The ioremapped HSTA MSI IO space */
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u32 __iomem *data;
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/* Physical address of HSTA MSI IO space */
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u64 address;
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struct msi_bitmap bmp;
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/* An array mapping offsets to hardware IRQs */
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int *irq_map;
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/* Number of hwirqs supported */
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int irq_count;
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};
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static struct ppc4xx_hsta_msi ppc4xx_hsta_msi;
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static int hsta_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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{
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struct msi_msg msg;
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struct msi_desc *entry;
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int irq, hwirq;
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u64 addr;
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list_for_each_entry(entry, &dev->msi_list, list) {
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irq = msi_bitmap_alloc_hwirqs(&ppc4xx_hsta_msi.bmp, 1);
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if (irq < 0) {
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pr_debug("%s: Failed to allocate msi interrupt\n",
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__func__);
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return irq;
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}
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hwirq = ppc4xx_hsta_msi.irq_map[irq];
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if (hwirq == NO_IRQ) {
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pr_err("%s: Failed mapping irq %d\n", __func__, irq);
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return -EINVAL;
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}
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/*
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* HSTA generates interrupts on writes to 128-bit aligned
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* addresses.
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*/
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addr = ppc4xx_hsta_msi.address + irq*0x10;
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msg.address_hi = upper_32_bits(addr);
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msg.address_lo = lower_32_bits(addr);
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/* Data is not used by the HSTA. */
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msg.data = 0;
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pr_debug("%s: Setup irq %d (0x%0llx)\n", __func__, hwirq,
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(((u64) msg.address_hi) << 32) | msg.address_lo);
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if (irq_set_msi_desc(hwirq, entry)) {
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pr_err(
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"%s: Invalid hwirq %d specified in device tree\n",
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__func__, hwirq);
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msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
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return -EINVAL;
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}
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write_msi_msg(hwirq, &msg);
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}
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return 0;
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}
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static int hsta_find_hwirq_offset(int hwirq)
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{
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int irq;
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/* Find the offset given the hwirq */
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for (irq = 0; irq < ppc4xx_hsta_msi.irq_count; irq++)
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if (ppc4xx_hsta_msi.irq_map[irq] == hwirq)
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return irq;
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return -EINVAL;
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}
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static void hsta_teardown_msi_irqs(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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int irq;
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list_for_each_entry(entry, &dev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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irq = hsta_find_hwirq_offset(entry->irq);
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/* entry->irq should always be in irq_map */
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BUG_ON(irq < 0);
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irq_set_msi_desc(entry->irq, NULL);
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msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
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pr_debug("%s: Teardown IRQ %u (index %u)\n", __func__,
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entry->irq, irq);
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}
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}
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static int hsta_msi_check_device(struct pci_dev *pdev, int nvec, int type)
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{
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/* We don't support MSI-X */
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if (type == PCI_CAP_ID_MSIX) {
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pr_debug("%s: MSI-X not supported.\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static int hsta_msi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *mem;
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int irq, ret, irq_count;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (IS_ERR(mem)) {
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dev_err(dev, "Unable to get mmio space\n");
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return -EINVAL;
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}
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irq_count = of_irq_count(dev->of_node);
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if (!irq_count) {
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dev_err(dev, "Unable to find IRQ range\n");
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return -EINVAL;
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}
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ppc4xx_hsta_msi.dev = dev;
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ppc4xx_hsta_msi.address = mem->start;
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ppc4xx_hsta_msi.data = ioremap(mem->start, resource_size(mem));
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ppc4xx_hsta_msi.irq_count = irq_count;
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if (IS_ERR(ppc4xx_hsta_msi.data)) {
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dev_err(dev, "Unable to map memory\n");
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return -ENOMEM;
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}
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ret = msi_bitmap_alloc(&ppc4xx_hsta_msi.bmp, irq_count, dev->of_node);
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if (ret)
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goto out;
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ppc4xx_hsta_msi.irq_map = kmalloc(sizeof(int) * irq_count, GFP_KERNEL);
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if (IS_ERR(ppc4xx_hsta_msi.irq_map)) {
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ret = -ENOMEM;
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goto out1;
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}
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/* Setup a mapping from irq offsets to hardware irq numbers */
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for (irq = 0; irq < irq_count; irq++) {
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ppc4xx_hsta_msi.irq_map[irq] =
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irq_of_parse_and_map(dev->of_node, irq);
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if (ppc4xx_hsta_msi.irq_map[irq] == NO_IRQ) {
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dev_err(dev, "Unable to map IRQ\n");
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ret = -EINVAL;
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goto out2;
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}
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}
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ppc_md.setup_msi_irqs = hsta_setup_msi_irqs;
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ppc_md.teardown_msi_irqs = hsta_teardown_msi_irqs;
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ppc_md.msi_check_device = hsta_msi_check_device;
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return 0;
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out2:
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kfree(ppc4xx_hsta_msi.irq_map);
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out1:
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msi_bitmap_free(&ppc4xx_hsta_msi.bmp);
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out:
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iounmap(ppc4xx_hsta_msi.data);
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return ret;
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}
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static const struct of_device_id hsta_msi_ids[] = {
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{
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.compatible = "ibm,hsta-msi",
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},
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{}
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};
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static struct platform_driver hsta_msi_driver = {
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.probe = hsta_msi_probe,
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.driver = {
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.name = "hsta-msi",
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.owner = THIS_MODULE,
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.of_match_table = hsta_msi_ids,
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},
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};
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static int hsta_msi_init(void)
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{
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return platform_driver_register(&hsta_msi_driver);
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}
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subsys_initcall(hsta_msi_init);
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