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120a56b01b
On mt753x_cpu_port_enable() there's code that enables flooding for the CPU port only. Since mt753x_cpu_port_enable() runs twice when both CPU ports are enabled, port 6 becomes the only port to forward the frames to. But port 5 is the active port, so no frames received from the user ports will be forwarded to port 5 which breaks network connectivity. Every bit of the BC_FFP, UNM_FFP, and UNU_FFP bits represents a port. Fix this issue by setting the bit that corresponds to the CPU port without overwriting the other bits. Clear the bits beforehand only for the MT7531 switch. According to the documents MT7621 Giga Switch Programming Guide v0.3 and MT7531 Reference Manual for Development Board v1.0, after reset, the BC_FFP, UNM_FFP, and UNU_FFP bits are set to 1 for MT7531, 0 for MT7530. The commit |
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b53 | ||
hirschmann | ||
microchip | ||
mv88e6xxx | ||
ocelot | ||
qca | ||
realtek | ||
sja1105 | ||
xrs700x | ||
bcm_sf2_cfp.c | ||
bcm_sf2_regs.h | ||
bcm_sf2.c | ||
bcm_sf2.h | ||
dsa_loop_bdinfo.c | ||
dsa_loop.c | ||
dsa_loop.h | ||
Kconfig | ||
lan9303_i2c.c | ||
lan9303_mdio.c | ||
lan9303-core.c | ||
lan9303.h | ||
lantiq_gswip.c | ||
lantiq_pce.h | ||
Makefile | ||
mt7530-mdio.c | ||
mt7530-mmio.c | ||
mt7530.c | ||
mt7530.h | ||
mv88e6060.c | ||
mv88e6060.h | ||
rzn1_a5psw.c | ||
rzn1_a5psw.h | ||
vitesse-vsc73xx-core.c | ||
vitesse-vsc73xx-platform.c | ||
vitesse-vsc73xx-spi.c | ||
vitesse-vsc73xx.h |