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927574e0e8
Add support for SM3 cipher in CryptoCell 713. Signed-off-by: Yael Chemla <yael.chemla@foss.arm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
136 lines
3.4 KiB
C
136 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
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#ifndef _CC_CRYPTO_CTX_H_
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#define _CC_CRYPTO_CTX_H_
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#include <linux/types.h>
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#define CC_DRV_DES_IV_SIZE 8
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#define CC_DRV_DES_BLOCK_SIZE 8
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#define CC_DRV_DES_ONE_KEY_SIZE 8
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#define CC_DRV_DES_DOUBLE_KEY_SIZE 16
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#define CC_DRV_DES_TRIPLE_KEY_SIZE 24
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#define CC_DRV_DES_KEY_SIZE_MAX CC_DRV_DES_TRIPLE_KEY_SIZE
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#define CC_AES_IV_SIZE 16
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#define CC_AES_IV_SIZE_WORDS (CC_AES_IV_SIZE >> 2)
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#define CC_AES_BLOCK_SIZE 16
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#define CC_AES_BLOCK_SIZE_WORDS 4
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#define CC_AES_128_BIT_KEY_SIZE 16
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#define CC_AES_128_BIT_KEY_SIZE_WORDS (CC_AES_128_BIT_KEY_SIZE >> 2)
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#define CC_AES_192_BIT_KEY_SIZE 24
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#define CC_AES_192_BIT_KEY_SIZE_WORDS (CC_AES_192_BIT_KEY_SIZE >> 2)
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#define CC_AES_256_BIT_KEY_SIZE 32
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#define CC_AES_256_BIT_KEY_SIZE_WORDS (CC_AES_256_BIT_KEY_SIZE >> 2)
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#define CC_AES_KEY_SIZE_MAX CC_AES_256_BIT_KEY_SIZE
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#define CC_AES_KEY_SIZE_WORDS_MAX (CC_AES_KEY_SIZE_MAX >> 2)
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#define CC_MD5_DIGEST_SIZE 16
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#define CC_SHA1_DIGEST_SIZE 20
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#define CC_SHA224_DIGEST_SIZE 28
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#define CC_SHA256_DIGEST_SIZE 32
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#define CC_SHA256_DIGEST_SIZE_IN_WORDS 8
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#define CC_SHA384_DIGEST_SIZE 48
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#define CC_SHA512_DIGEST_SIZE 64
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#define CC_SHA1_BLOCK_SIZE 64
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#define CC_SHA1_BLOCK_SIZE_IN_WORDS 16
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#define CC_MD5_BLOCK_SIZE 64
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#define CC_MD5_BLOCK_SIZE_IN_WORDS 16
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#define CC_SHA224_BLOCK_SIZE 64
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#define CC_SHA256_BLOCK_SIZE 64
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#define CC_SHA256_BLOCK_SIZE_IN_WORDS 16
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#define CC_SHA1_224_256_BLOCK_SIZE 64
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#define CC_SHA384_BLOCK_SIZE 128
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#define CC_SHA512_BLOCK_SIZE 128
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#define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE
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#define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/
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#define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX
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#define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX
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enum drv_engine_type {
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DRV_ENGINE_NULL = 0,
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DRV_ENGINE_AES = 1,
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DRV_ENGINE_DES = 2,
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DRV_ENGINE_HASH = 3,
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DRV_ENGINE_RC4 = 4,
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DRV_ENGINE_DOUT = 5,
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DRV_ENGINE_RESERVE32B = S32_MAX,
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};
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enum drv_crypto_alg {
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DRV_CRYPTO_ALG_NULL = -1,
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DRV_CRYPTO_ALG_AES = 0,
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DRV_CRYPTO_ALG_DES = 1,
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DRV_CRYPTO_ALG_HASH = 2,
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DRV_CRYPTO_ALG_C2 = 3,
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DRV_CRYPTO_ALG_HMAC = 4,
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DRV_CRYPTO_ALG_AEAD = 5,
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DRV_CRYPTO_ALG_BYPASS = 6,
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DRV_CRYPTO_ALG_NUM = 7,
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DRV_CRYPTO_ALG_RESERVE32B = S32_MAX
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};
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enum drv_crypto_direction {
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DRV_CRYPTO_DIRECTION_NULL = -1,
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DRV_CRYPTO_DIRECTION_ENCRYPT = 0,
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DRV_CRYPTO_DIRECTION_DECRYPT = 1,
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DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3,
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DRV_CRYPTO_DIRECTION_RESERVE32B = S32_MAX
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};
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enum drv_cipher_mode {
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DRV_CIPHER_NULL_MODE = -1,
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DRV_CIPHER_ECB = 0,
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DRV_CIPHER_CBC = 1,
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DRV_CIPHER_CTR = 2,
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DRV_CIPHER_CBC_MAC = 3,
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DRV_CIPHER_XTS = 4,
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DRV_CIPHER_XCBC_MAC = 5,
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DRV_CIPHER_OFB = 6,
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DRV_CIPHER_CMAC = 7,
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DRV_CIPHER_CCM = 8,
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DRV_CIPHER_CBC_CTS = 11,
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DRV_CIPHER_GCTR = 12,
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DRV_CIPHER_ESSIV = 13,
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DRV_CIPHER_BITLOCKER = 14,
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DRV_CIPHER_RESERVE32B = S32_MAX
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};
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enum drv_hash_mode {
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DRV_HASH_NULL = -1,
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DRV_HASH_SHA1 = 0,
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DRV_HASH_SHA256 = 1,
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DRV_HASH_SHA224 = 2,
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DRV_HASH_SHA512 = 3,
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DRV_HASH_SHA384 = 4,
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DRV_HASH_MD5 = 5,
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DRV_HASH_CBC_MAC = 6,
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DRV_HASH_XCBC_MAC = 7,
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DRV_HASH_CMAC = 8,
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DRV_HASH_SM3 = 9,
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DRV_HASH_MODE_NUM = 10,
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DRV_HASH_RESERVE32B = S32_MAX
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};
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enum drv_hash_hw_mode {
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DRV_HASH_HW_MD5 = 0,
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DRV_HASH_HW_SHA1 = 1,
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DRV_HASH_HW_SHA256 = 2,
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DRV_HASH_HW_SHA224 = 10,
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DRV_HASH_HW_SHA512 = 4,
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DRV_HASH_HW_SHA384 = 12,
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DRV_HASH_HW_GHASH = 6,
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DRV_HASH_HW_SM3 = 14,
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DRV_HASH_HW_RESERVE32B = S32_MAX
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};
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#endif /* _CC_CRYPTO_CTX_H_ */
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