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5b0e2cb020
Non-highlights: - Five fixes for the >128T address space handling, both to fix bugs in our implementation and to bring the semantics exactly into line with x86. Highlights: - Support for a new OPAL call on bare metal machines which gives us a true NMI (ie. is not masked by MSR[EE]=0) for debugging etc. - Support for Power9 DD2 in the CXL driver. - Improvements to machine check handling so that uncorrectable errors can be reported into the generic memory_failure() machinery. - Some fixes and improvements for VPHN, which is used under PowerVM to notify the Linux partition of topology changes. - Plumbing to enable TM (transactional memory) without suspend on some Power9 processors (PPC_FEATURE2_HTM_NO_SUSPEND). - Support for emulating vector loads form cache-inhibited memory, on some Power9 revisions. - Disable the fast-endian switch "syscall" by default (behind a CONFIG), we believe it has never had any users. - A major rework of the API drivers use when initiating and waiting for long running operations performed by OPAL firmware, and changes to the powernv_flash driver to use the new API. - Several fixes for the handling of FP/VMX/VSX while processes are using transactional memory. - Optimisations of TLB range flushes when using the radix MMU on Power9. - Improvements to the VAS facility used to access coprocessors on Power9, and related improvements to the way the NX crypto driver handles requests. - Implementation of PMEM_API and UACCESS_FLUSHCACHE for 64-bit. Thanks to: Alexey Kardashevskiy, Alistair Popple, Allen Pais, Andrew Donnellan, Aneesh Kumar K.V, Arnd Bergmann, Balbir Singh, Benjamin Herrenschmidt, Breno Leitao, Christophe Leroy, Christophe Lombard, Cyril Bur, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven, Guilherme G. Piccoli, Gustavo Romero, Haren Myneni, Joel Stanley, Kamalesh Babulal, Kautuk Consul, Markus Elfring, Masami Hiramatsu, Michael Bringmann, Michael Neuling, Michal Suchanek, Naveen N. Rao, Nicholas Piggin, Oliver O'Halloran, Paul Mackerras, Pedro Miraglia Franco de Carvalho, Philippe Bergheaud, Sandipan Das, Seth Forshee, Shriya, Stephen Rothwell, Stewart Smith, Sukadev Bhattiprolu, Tyrel Datwyler, Vaibhav Jain, Vaidyanathan Srinivasan, William A. Kennington III. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaDXGuAAoJEFHr6jzI4aWAEqwP/0TA35KFAK6wqfkCf67z4q+O I+5piI4eDV4jdCakfoIN1JfjhQRULNePSoCHTccan30mu/bm30p69xtOLL2/h5xH Mhz/eDBAOo0lrT20nyZfYMW3FnM66wnNf++qJ0O+8L052r4WOB02J0k1uM1ST01D 5Lb5mUoxRLRzCgKRYAYWJifn+IFPUB9NMsvMTym94krAFlIjIzMEQXhDoln+jJMr QmY5f1BTA/fLfXobn0zwoc/C1oa2PUtxd+rxbwGrLoZ6G843mMqUi90SMr5ybhXp RzepnBTj4by3vOsnk/X1mANyaZfLsunp75FwnjHdPzKrAS/TuPp8D/iSxxE/PzEq cLwJFBnFXSgQMefDErXxhHSDz2dAg5r14rsTpDcq2Ko8TPV4rPsuSfmbd9Txekb0 yWHsjoJUBBMl2QcWqIHl+AlV8j1RklF6solcTBcGnH1CZJMfa05VKXV7xGEvOHa0 RJ+/xPyR9KjoB/SUp++9Vmx/M6SwQYFOJlr3Zpg9LNtR8WpoPYu1E6eO+u1Hhzny eJqaNstH+i+VdY9eqszkAsEBh8o9M/+b+7Wx7TetvU+v368CbXtgFYs9qy2oZjPF t9sY/BHaHZ8eZ7I00an77a0fVV5B1PVASUtIz5CqkwGpMvX6Z6W2K/XUUFI61kuu E06HS6Ht8UPJAzrAPUMl =Rq81 -----END PGP SIGNATURE----- Merge tag 'powerpc-4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc updates from Michael Ellerman: "A bit of a small release, I suspect in part due to me travelling for KS. But my backlog of patches to review is smaller than usual, so I think in part folks just didn't send as much this cycle. Non-highlights: - Five fixes for the >128T address space handling, both to fix bugs in our implementation and to bring the semantics exactly into line with x86. Highlights: - Support for a new OPAL call on bare metal machines which gives us a true NMI (ie. is not masked by MSR[EE]=0) for debugging etc. - Support for Power9 DD2 in the CXL driver. - Improvements to machine check handling so that uncorrectable errors can be reported into the generic memory_failure() machinery. - Some fixes and improvements for VPHN, which is used under PowerVM to notify the Linux partition of topology changes. - Plumbing to enable TM (transactional memory) without suspend on some Power9 processors (PPC_FEATURE2_HTM_NO_SUSPEND). - Support for emulating vector loads form cache-inhibited memory, on some Power9 revisions. - Disable the fast-endian switch "syscall" by default (behind a CONFIG), we believe it has never had any users. - A major rework of the API drivers use when initiating and waiting for long running operations performed by OPAL firmware, and changes to the powernv_flash driver to use the new API. - Several fixes for the handling of FP/VMX/VSX while processes are using transactional memory. - Optimisations of TLB range flushes when using the radix MMU on Power9. - Improvements to the VAS facility used to access coprocessors on Power9, and related improvements to the way the NX crypto driver handles requests. - Implementation of PMEM_API and UACCESS_FLUSHCACHE for 64-bit. Thanks to: Alexey Kardashevskiy, Alistair Popple, Allen Pais, Andrew Donnellan, Aneesh Kumar K.V, Arnd Bergmann, Balbir Singh, Benjamin Herrenschmidt, Breno Leitao, Christophe Leroy, Christophe Lombard, Cyril Bur, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven, Guilherme G. Piccoli, Gustavo Romero, Haren Myneni, Joel Stanley, Kamalesh Babulal, Kautuk Consul, Markus Elfring, Masami Hiramatsu, Michael Bringmann, Michael Neuling, Michal Suchanek, Naveen N. Rao, Nicholas Piggin, Oliver O'Halloran, Paul Mackerras, Pedro Miraglia Franco de Carvalho, Philippe Bergheaud, Sandipan Das, Seth Forshee, Shriya, Stephen Rothwell, Stewart Smith, Sukadev Bhattiprolu, Tyrel Datwyler, Vaibhav Jain, Vaidyanathan Srinivasan, and William A. Kennington III" * tag 'powerpc-4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (151 commits) powerpc/64s: Fix Power9 DD2.0 workarounds by adding DD2.1 feature powerpc/64s: Fix masking of SRR1 bits on instruction fault powerpc/64s: mm_context.addr_limit is only used on hash powerpc/64s/radix: Fix 128TB-512TB virtual address boundary case allocation powerpc/64s/hash: Allow MAP_FIXED allocations to cross 128TB boundary powerpc/64s/hash: Fix fork() with 512TB process address space powerpc/64s/hash: Fix 128TB-512TB virtual address boundary case allocation powerpc/64s/hash: Fix 512T hint detection to use >= 128T powerpc: Fix DABR match on hash based systems powerpc/signal: Properly handle return value from uprobe_deny_signal() powerpc/fadump: use kstrtoint to handle sysfs store powerpc/lib: Implement UACCESS_FLUSHCACHE API powerpc/lib: Implement PMEM API powerpc/powernv/npu: Don't explicitly flush nmmu tlb powerpc/powernv/npu: Use flush_all_mm() instead of flush_tlb_mm() powerpc/powernv/idle: Round up latency and residency values powerpc/kprobes: refactor kprobe_lookup_name for safer string operations powerpc/kprobes: Blacklist emulate_update_regs() from kprobes powerpc/kprobes: Do not disable interrupts for optprobes and kprobes_on_ftrace powerpc/kprobes: Disable preemption before invoking probe handler for optprobes ...
271 lines
6.2 KiB
C
271 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* temp.c Thermal management for cpu's with Thermal Assist Units
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*
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* Written by Troy Benjegerdes <hozer@drgw.net>
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*
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* TODO:
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* dynamic power management to limit peak CPU temp (using ICTC)
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* calibration???
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*
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* Silly, crazy ideas: use cpu load (from scheduler) and ICTC to extend battery
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* life in portables, and add a 'performance/watt' metric somewhere in /proc
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*/
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#include <linux/errno.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/reg.h>
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#include <asm/nvram.h>
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#include <asm/cache.h>
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#include <asm/8xx_immap.h>
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#include <asm/machdep.h>
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static struct tau_temp
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{
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int interrupts;
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unsigned char low;
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unsigned char high;
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unsigned char grew;
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} tau[NR_CPUS];
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struct timer_list tau_timer;
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#undef DEBUG
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/* TODO: put these in a /proc interface, with some sanity checks, and maybe
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* dynamic adjustment to minimize # of interrupts */
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/* configurable values for step size and how much to expand the window when
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* we get an interrupt. These are based on the limit that was out of range */
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#define step_size 2 /* step size when temp goes out of range */
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#define window_expand 1 /* expand the window by this much */
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/* configurable values for shrinking the window */
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#define shrink_timer 2*HZ /* period between shrinking the window */
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#define min_window 2 /* minimum window size, degrees C */
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void set_thresholds(unsigned long cpu)
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{
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#ifdef CONFIG_TAU_INT
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/*
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* setup THRM1,
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* threshold, valid bit, enable interrupts, interrupt when below threshold
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*/
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mtspr(SPRN_THRM1, THRM1_THRES(tau[cpu].low) | THRM1_V | THRM1_TIE | THRM1_TID);
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/* setup THRM2,
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* threshold, valid bit, enable interrupts, interrupt when above threshold
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*/
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mtspr (SPRN_THRM2, THRM1_THRES(tau[cpu].high) | THRM1_V | THRM1_TIE);
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#else
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/* same thing but don't enable interrupts */
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mtspr(SPRN_THRM1, THRM1_THRES(tau[cpu].low) | THRM1_V | THRM1_TID);
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mtspr(SPRN_THRM2, THRM1_THRES(tau[cpu].high) | THRM1_V);
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#endif
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}
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void TAUupdate(int cpu)
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{
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unsigned thrm;
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#ifdef DEBUG
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printk("TAUupdate ");
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#endif
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/* if both thresholds are crossed, the step_sizes cancel out
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* and the window winds up getting expanded twice. */
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if((thrm = mfspr(SPRN_THRM1)) & THRM1_TIV){ /* is valid? */
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if(thrm & THRM1_TIN){ /* crossed low threshold */
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if (tau[cpu].low >= step_size){
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tau[cpu].low -= step_size;
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tau[cpu].high -= (step_size - window_expand);
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}
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tau[cpu].grew = 1;
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#ifdef DEBUG
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printk("low threshold crossed ");
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#endif
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}
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}
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if((thrm = mfspr(SPRN_THRM2)) & THRM1_TIV){ /* is valid? */
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if(thrm & THRM1_TIN){ /* crossed high threshold */
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if (tau[cpu].high <= 127-step_size){
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tau[cpu].low += (step_size - window_expand);
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tau[cpu].high += step_size;
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}
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tau[cpu].grew = 1;
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#ifdef DEBUG
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printk("high threshold crossed ");
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#endif
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}
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}
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#ifdef DEBUG
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printk("grew = %d\n", tau[cpu].grew);
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#endif
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#ifndef CONFIG_TAU_INT /* tau_timeout will do this if not using interrupts */
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set_thresholds(cpu);
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#endif
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}
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#ifdef CONFIG_TAU_INT
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/*
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* TAU interrupts - called when we have a thermal assist unit interrupt
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* with interrupts disabled
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*/
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void TAUException(struct pt_regs * regs)
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{
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int cpu = smp_processor_id();
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irq_enter();
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tau[cpu].interrupts++;
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TAUupdate(cpu);
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irq_exit();
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}
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#endif /* CONFIG_TAU_INT */
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static void tau_timeout(void * info)
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{
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int cpu;
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unsigned long flags;
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int size;
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int shrink;
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/* disabling interrupts *should* be okay */
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local_irq_save(flags);
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cpu = smp_processor_id();
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#ifndef CONFIG_TAU_INT
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TAUupdate(cpu);
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#endif
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size = tau[cpu].high - tau[cpu].low;
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if (size > min_window && ! tau[cpu].grew) {
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/* do an exponential shrink of half the amount currently over size */
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shrink = (2 + size - min_window) / 4;
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if (shrink) {
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tau[cpu].low += shrink;
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tau[cpu].high -= shrink;
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} else { /* size must have been min_window + 1 */
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tau[cpu].low += 1;
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#if 1 /* debug */
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if ((tau[cpu].high - tau[cpu].low) != min_window){
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printk(KERN_ERR "temp.c: line %d, logic error\n", __LINE__);
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}
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#endif
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}
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}
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tau[cpu].grew = 0;
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set_thresholds(cpu);
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/*
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* Do the enable every time, since otherwise a bunch of (relatively)
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* complex sleep code needs to be added. One mtspr every time
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* tau_timeout is called is probably not a big deal.
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*
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* Enable thermal sensor and set up sample interval timer
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* need 20 us to do the compare.. until a nice 'cpu_speed' function
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* call is implemented, just assume a 500 mhz clock. It doesn't really
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* matter if we take too long for a compare since it's all interrupt
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* driven anyway.
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*
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* use a extra long time.. (60 us @ 500 mhz)
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*/
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mtspr(SPRN_THRM3, THRM3_SITV(500*60) | THRM3_E);
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local_irq_restore(flags);
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}
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static void tau_timeout_smp(unsigned long unused)
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{
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/* schedule ourselves to be run again */
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mod_timer(&tau_timer, jiffies + shrink_timer) ;
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on_each_cpu(tau_timeout, NULL, 0);
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}
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/*
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* setup the TAU
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*
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* Set things up to use THRM1 as a temperature lower bound, and THRM2 as an upper bound.
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* Start off at zero
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*/
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int tau_initialized = 0;
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void __init TAU_init_smp(void * info)
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{
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unsigned long cpu = smp_processor_id();
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/* set these to a reasonable value and let the timer shrink the
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* window */
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tau[cpu].low = 5;
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tau[cpu].high = 120;
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set_thresholds(cpu);
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}
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int __init TAU_init(void)
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{
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/* We assume in SMP that if one CPU has TAU support, they
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* all have it --BenH
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*/
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if (!cpu_has_feature(CPU_FTR_TAU)) {
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printk("Thermal assist unit not available\n");
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tau_initialized = 0;
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return 1;
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}
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/* first, set up the window shrinking timer */
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setup_timer(&tau_timer, tau_timeout_smp, 0UL);
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tau_timer.expires = jiffies + shrink_timer;
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add_timer(&tau_timer);
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on_each_cpu(TAU_init_smp, NULL, 0);
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printk("Thermal assist unit ");
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#ifdef CONFIG_TAU_INT
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printk("using interrupts, ");
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#else
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printk("using timers, ");
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#endif
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printk("shrink_timer: %d jiffies\n", shrink_timer);
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tau_initialized = 1;
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return 0;
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}
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__initcall(TAU_init);
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/*
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* return current temp
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*/
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u32 cpu_temp_both(unsigned long cpu)
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{
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return ((tau[cpu].high << 16) | tau[cpu].low);
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}
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int cpu_temp(unsigned long cpu)
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{
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return ((tau[cpu].high + tau[cpu].low) / 2);
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}
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int tau_interrupts(unsigned long cpu)
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{
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return (tau[cpu].interrupts);
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}
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