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Add support for the resets on i.MX8MP Audio Block Control module, which includes the EARC PHY software reset and EARC controller software reset. The reset controller is created using the auxiliary device framework and set up in the clock driver. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/1719200345-32006-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2024 NXP
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*/
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#include <linux/auxiliary_bus.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/reset-controller.h>
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#define EARC 0x200
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#define EARC_RESET_MASK 0x3
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struct imx8mp_audiomix_reset {
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struct reset_controller_dev rcdev;
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spinlock_t lock; /* protect register read-modify-write cycle */
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void __iomem *base;
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};
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static struct imx8mp_audiomix_reset *to_imx8mp_audiomix_reset(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct imx8mp_audiomix_reset, rcdev);
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}
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static int imx8mp_audiomix_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct imx8mp_audiomix_reset *priv = to_imx8mp_audiomix_reset(rcdev);
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void __iomem *reg_addr = priv->base;
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unsigned int mask, reg;
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unsigned long flags;
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mask = BIT(id);
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spin_lock_irqsave(&priv->lock, flags);
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reg = readl(reg_addr + EARC);
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writel(reg & ~mask, reg_addr + EARC);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int imx8mp_audiomix_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct imx8mp_audiomix_reset *priv = to_imx8mp_audiomix_reset(rcdev);
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void __iomem *reg_addr = priv->base;
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unsigned int mask, reg;
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unsigned long flags;
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mask = BIT(id);
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spin_lock_irqsave(&priv->lock, flags);
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reg = readl(reg_addr + EARC);
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writel(reg | mask, reg_addr + EARC);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static const struct reset_control_ops imx8mp_audiomix_reset_ops = {
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.assert = imx8mp_audiomix_reset_assert,
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.deassert = imx8mp_audiomix_reset_deassert,
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};
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static int imx8mp_audiomix_reset_probe(struct auxiliary_device *adev,
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const struct auxiliary_device_id *id)
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{
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struct imx8mp_audiomix_reset *priv;
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struct device *dev = &adev->dev;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->lock);
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priv->rcdev.owner = THIS_MODULE;
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priv->rcdev.nr_resets = fls(EARC_RESET_MASK);
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priv->rcdev.ops = &imx8mp_audiomix_reset_ops;
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priv->rcdev.of_node = dev->parent->of_node;
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priv->rcdev.dev = dev;
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priv->rcdev.of_reset_n_cells = 1;
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priv->base = of_iomap(dev->parent->of_node, 0);
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if (!priv->base)
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return -ENOMEM;
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dev_set_drvdata(dev, priv);
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ret = devm_reset_controller_register(dev, &priv->rcdev);
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if (ret)
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goto out_unmap;
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return 0;
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out_unmap:
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iounmap(priv->base);
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return ret;
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}
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static void imx8mp_audiomix_reset_remove(struct auxiliary_device *adev)
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{
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struct imx8mp_audiomix_reset *priv = dev_get_drvdata(&adev->dev);
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iounmap(priv->base);
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}
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static const struct auxiliary_device_id imx8mp_audiomix_reset_ids[] = {
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{
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.name = "clk_imx8mp_audiomix.reset",
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},
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{ }
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};
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MODULE_DEVICE_TABLE(auxiliary, imx8mp_audiomix_reset_ids);
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static struct auxiliary_driver imx8mp_audiomix_reset_driver = {
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.probe = imx8mp_audiomix_reset_probe,
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.remove = imx8mp_audiomix_reset_remove,
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.id_table = imx8mp_audiomix_reset_ids,
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};
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module_auxiliary_driver(imx8mp_audiomix_reset_driver);
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MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
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MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller reset driver");
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MODULE_LICENSE("GPL");
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