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a55360e458
This patch moves partialy rx code into iwl-rx.c as part of iwlcore. The second part of the code can be merged only with moving of tx code as well. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
372 lines
12 KiB
C
372 lines
12 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project, as well
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* as portions of the ieee80211 subsystem header files.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* James P. Ketrenos <ipw2100-admin@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#include <net/mac80211.h>
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#include "iwl-eeprom.h"
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-sta.h"
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#include "iwl-io.h"
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#include "iwl-helpers.h"
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/************************** RX-FUNCTIONS ****************************/
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/*
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* Rx theory of operation
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*
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* Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
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* each of which point to Receive Buffers to be filled by the NIC. These get
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* used not only for Rx frames, but for any command response or notification
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* from the NIC. The driver and NIC manage the Rx buffers by means
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* of indexes into the circular buffer.
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*
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* Rx Queue Indexes
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* The host/firmware share two index registers for managing the Rx buffers.
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*
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* The READ index maps to the first position that the firmware may be writing
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* to -- the driver can read up to (but not including) this position and get
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* good data.
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* The READ index is managed by the firmware once the card is enabled.
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*
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* The WRITE index maps to the last position the driver has read from -- the
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* position preceding WRITE is the last slot the firmware can place a packet.
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*
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* The queue is empty (no good data) if WRITE = READ - 1, and is full if
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* WRITE = READ.
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*
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* During initialization, the host sets up the READ queue position to the first
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* INDEX position, and WRITE to the last (READ - 1 wrapped)
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*
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* When the firmware places a packet in a buffer, it will advance the READ index
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* and fire the RX interrupt. The driver can then query the READ index and
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* process as many packets as possible, moving the WRITE index forward as it
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* resets the Rx queue buffers with new memory.
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*
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* The management in the driver is as follows:
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* + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
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* iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
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* to replenish the iwl->rxq->rx_free.
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* + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
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* iwl->rxq is replenished and the READ INDEX is updated (updating the
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* 'processed' and 'read' driver indexes as well)
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* + A received packet is processed and handed to the kernel network stack,
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* detached from the iwl->rxq. The driver 'processed' index is updated.
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* + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
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* list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
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* INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
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* were enough free buffers and RX_STALLED is set it is cleared.
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*
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*
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* Driver sequence:
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*
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* iwl_rx_queue_alloc() Allocates rx_free
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* iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
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* iwl_rx_queue_restock
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* iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
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* queue, updates firmware pointers, and updates
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* the WRITE index. If insufficient rx_free buffers
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* are available, schedules iwl_rx_replenish
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*
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* -- enable interrupts --
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* ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
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* READ INDEX, detaching the SKB from the pool.
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* Moves the packet buffer from queue to rx_used.
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* Calls iwl_rx_queue_restock to refill any empty
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* slots.
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* ...
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*
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*/
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/**
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* iwl_rx_queue_space - Return number of free slots available in queue.
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*/
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int iwl_rx_queue_space(const struct iwl_rx_queue *q)
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{
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int s = q->read - q->write;
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if (s <= 0)
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s += RX_QUEUE_SIZE;
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/* keep some buffer to not confuse full and empty queue */
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s -= 2;
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if (s < 0)
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s = 0;
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return s;
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}
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EXPORT_SYMBOL(iwl_rx_queue_space);
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/**
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* iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
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*/
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int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
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{
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u32 reg = 0;
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&q->lock, flags);
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if (q->need_update == 0)
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goto exit_unlock;
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/* If power-saving is in use, make sure device is awake */
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if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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iwl_set_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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goto exit_unlock;
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}
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ret = iwl_grab_nic_access(priv);
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if (ret)
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goto exit_unlock;
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/* Device expects a multiple of 8 */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
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q->write & ~0x7);
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iwl_release_nic_access(priv);
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/* Else device is assumed to be awake */
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} else
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/* Device expects a multiple of 8 */
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iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
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q->need_update = 0;
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exit_unlock:
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spin_unlock_irqrestore(&q->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
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/**
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* iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
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*/
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static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
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dma_addr_t dma_addr)
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{
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return cpu_to_le32((u32)(dma_addr >> 8));
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}
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/**
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* iwl_rx_queue_restock - refill RX queue from pre-allocated pool
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*
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* If there are slots in the RX queue that need to be restocked,
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* and we have free pre-allocated buffers, fill the ranks as much
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* as we can, pulling from rx_free.
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*
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* This moves the 'write' index forward to catch up with 'processed', and
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* also updates the memory address in the firmware to reference the new
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* target buffer.
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*/
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int iwl_rx_queue_restock(struct iwl_priv *priv)
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{
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struct iwl_rx_queue *rxq = &priv->rxq;
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struct list_head *element;
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struct iwl_rx_mem_buffer *rxb;
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unsigned long flags;
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int write;
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int ret = 0;
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spin_lock_irqsave(&rxq->lock, flags);
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write = rxq->write & ~0x7;
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while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
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/* Get next free Rx buffer, remove from free list */
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element = rxq->rx_free.next;
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rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
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list_del(element);
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/* Point to Rx buffer via next RBD in circular buffer */
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rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->dma_addr);
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rxq->queue[rxq->write] = rxb;
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rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
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rxq->free_count--;
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}
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spin_unlock_irqrestore(&rxq->lock, flags);
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/* If the pre-allocated buffer pool is dropping low, schedule to
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* refill it */
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if (rxq->free_count <= RX_LOW_WATERMARK)
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queue_work(priv->workqueue, &priv->rx_replenish);
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/* If we've added more space for the firmware to place data, tell it.
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* Increment device's write pointer in multiples of 8. */
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if ((write != (rxq->write & ~0x7))
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|| (abs(rxq->write - rxq->read) > 7)) {
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spin_lock_irqsave(&rxq->lock, flags);
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rxq->need_update = 1;
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spin_unlock_irqrestore(&rxq->lock, flags);
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ret = iwl_rx_queue_update_write_ptr(priv, rxq);
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}
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return ret;
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}
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EXPORT_SYMBOL(iwl_rx_queue_restock);
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/**
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* iwl_rx_replenish - Move all used packet from rx_used to rx_free
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*
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* When moving to rx_free an SKB is allocated for the slot.
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*
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* Also restock the Rx queue via iwl_rx_queue_restock.
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* This is called as a scheduled work item (except for during initialization)
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*/
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void iwl_rx_allocate(struct iwl_priv *priv)
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{
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struct iwl_rx_queue *rxq = &priv->rxq;
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struct list_head *element;
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struct iwl_rx_mem_buffer *rxb;
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unsigned long flags;
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spin_lock_irqsave(&rxq->lock, flags);
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while (!list_empty(&rxq->rx_used)) {
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element = rxq->rx_used.next;
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rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
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/* Alloc a new receive buffer */
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rxb->skb = alloc_skb(priv->hw_params.rx_buf_size,
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__GFP_NOWARN | GFP_ATOMIC);
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if (!rxb->skb) {
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if (net_ratelimit())
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printk(KERN_CRIT DRV_NAME
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": Can not allocate SKB buffers\n");
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/* We don't reschedule replenish work here -- we will
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* call the restock method and if it still needs
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* more buffers it will schedule replenish */
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break;
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}
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priv->alloc_rxb_skb++;
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list_del(element);
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/* Get physical address of RB/SKB */
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rxb->dma_addr =
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pci_map_single(priv->pci_dev, rxb->skb->data,
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priv->hw_params.rx_buf_size, PCI_DMA_FROMDEVICE);
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list_add_tail(&rxb->list, &rxq->rx_free);
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rxq->free_count++;
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}
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spin_unlock_irqrestore(&rxq->lock, flags);
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}
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EXPORT_SYMBOL(iwl_rx_allocate);
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void iwl_rx_replenish(struct iwl_priv *priv)
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{
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unsigned long flags;
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iwl_rx_allocate(priv);
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spin_lock_irqsave(&priv->lock, flags);
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iwl_rx_queue_restock(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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EXPORT_SYMBOL(iwl_rx_replenish);
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/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
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* If an SKB has been detached, the POOL needs to have its SKB set to NULL
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* This free routine walks the list of POOL entries and if SKB is set to
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* non NULL it is unmapped and freed
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*/
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void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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{
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int i;
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for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
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if (rxq->pool[i].skb != NULL) {
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pci_unmap_single(priv->pci_dev,
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rxq->pool[i].dma_addr,
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priv->hw_params.rx_buf_size,
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PCI_DMA_FROMDEVICE);
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dev_kfree_skb(rxq->pool[i].skb);
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}
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}
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pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
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rxq->dma_addr);
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rxq->bd = NULL;
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}
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EXPORT_SYMBOL(iwl_rx_queue_free);
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int iwl_rx_queue_alloc(struct iwl_priv *priv)
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{
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struct iwl_rx_queue *rxq = &priv->rxq;
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struct pci_dev *dev = priv->pci_dev;
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int i;
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spin_lock_init(&rxq->lock);
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INIT_LIST_HEAD(&rxq->rx_free);
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INIT_LIST_HEAD(&rxq->rx_used);
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/* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
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rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
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if (!rxq->bd)
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return -ENOMEM;
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/* Fill the rx_used queue with _all_ of the Rx buffers */
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for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
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list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
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/* Set us so that we have processed and used all buffers, but have
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* not restocked the Rx queue with fresh buffers */
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rxq->read = rxq->write = 0;
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rxq->free_count = 0;
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rxq->need_update = 0;
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return 0;
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}
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EXPORT_SYMBOL(iwl_rx_queue_alloc);
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void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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{
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unsigned long flags;
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int i;
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spin_lock_irqsave(&rxq->lock, flags);
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INIT_LIST_HEAD(&rxq->rx_free);
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INIT_LIST_HEAD(&rxq->rx_used);
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/* Fill the rx_used queue with _all_ of the Rx buffers */
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for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
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/* In the reset function, these buffers may have been allocated
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* to an SKB, so we need to unmap and free potential storage */
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if (rxq->pool[i].skb != NULL) {
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pci_unmap_single(priv->pci_dev,
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rxq->pool[i].dma_addr,
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priv->hw_params.rx_buf_size,
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PCI_DMA_FROMDEVICE);
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priv->alloc_rxb_skb--;
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dev_kfree_skb(rxq->pool[i].skb);
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rxq->pool[i].skb = NULL;
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}
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list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
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}
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/* Set us so that we have processed and used all buffers, but have
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* not restocked the Rx queue with fresh buffers */
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rxq->read = rxq->write = 0;
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rxq->free_count = 0;
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spin_unlock_irqrestore(&rxq->lock, flags);
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}
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EXPORT_SYMBOL(iwl_rx_queue_reset);
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