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165 lines
6.1 KiB
C
165 lines
6.1 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/irqs.h
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_IRQS_H
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#define __ASM_MACH_IRQS_H
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#ifdef CONFIG_PXA_HAVE_ISA_IRQS
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#define PXA_ISA_IRQ(x) (x)
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#define PXA_ISA_IRQ_NUM (16)
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#else
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#define PXA_ISA_IRQ_NUM (0)
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#endif
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#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x))
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
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#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
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#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
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#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */
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#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
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#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
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#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
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#endif
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#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
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#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
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#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
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#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */
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#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
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#define IRQ_USB PXA_IRQ(11) /* USB Service */
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#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
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#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */
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#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
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#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
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#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
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#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */
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#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */
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#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
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#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
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#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
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#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
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#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
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#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
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#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */
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#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */
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#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */
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#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */
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#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */
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#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */
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#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */
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#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
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#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
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#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
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#endif
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#ifdef CONFIG_PXA3xx
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#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */
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#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
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#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
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#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
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#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
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#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller */
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#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
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#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
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#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
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#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */
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#define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */
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#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */
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#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
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#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
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#endif
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#ifdef CONFIG_CPU_PXA935
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#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */
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#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */
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#define IRQ_MMC3_PXA935 PXA_IRQ(72) /* MMC3 Controller (PXA935) */
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#define IRQ_MMC4_PXA935 PXA_IRQ(73) /* MMC4 Controller (PXA935) */
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#define IRQ_MMC5_PXA935 PXA_IRQ(74) /* MMC5 Controller (PXA935) */
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#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
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#endif
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#ifdef CONFIG_CPU_PXA930
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#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
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#define IRQ_ACIPC0 PXA_IRQ(5)
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#define IRQ_ACIPC1 PXA_IRQ(40)
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#define IRQ_ACIPC2 PXA_IRQ(19)
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#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball */
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#endif
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#ifdef CONFIG_CPU_PXA950
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#define IRQ_GC500 PXA_IRQ(70) /* Graphics Controller (PXA950) */
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#endif
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#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
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#define PXA_GPIO_IRQ_NUM (192)
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#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
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#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
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#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
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#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
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/*
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* The following interrupts are for board specific purposes. Since
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* the kernel can only run on one machine at a time, we can re-use
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* these. There will be 16 IRQs by default. If it is not enough,
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* IRQ_BOARD_END is allowed be customized for each board, but keep
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* the numbers within sensible limits and in descending order, so
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* when multiple config options are selected, the maximum will be
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* used.
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*/
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#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
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#if defined(CONFIG_MACH_H4700)
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#define IRQ_BOARD_END (IRQ_BOARD_START + 70)
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#elif defined(CONFIG_MACH_ZYLONITE)
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#define IRQ_BOARD_END (IRQ_BOARD_START + 32)
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#elif defined(CONFIG_PXA_EZX)
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#define IRQ_BOARD_END (IRQ_BOARD_START + 23)
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#else
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#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
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#endif
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/*
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* Figure out the MAX IRQ number.
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*
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* If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
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* If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
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* Otherwise, we have the standard IRQs only.
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*/
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#ifdef CONFIG_SA1111
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#define NR_IRQS (IRQ_BOARD_END + 55)
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#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
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#define NR_IRQS (IRQ_BOARD_END)
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#else
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#define NR_IRQS (IRQ_BOARD_START)
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#endif
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/* add IT8152 IRQs beyond BOARD_END */
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#ifdef CONFIG_PCI_HOST_ITE8152
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#define IT8152_LAST_IRQ (IRQ_BOARD_END + 40)
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#if NR_IRQS < (IT8152_LAST_IRQ+1)
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#undef NR_IRQS
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#define NR_IRQS (IT8152_LAST_IRQ+1)
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#endif
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#endif /* CONFIG_PCI_HOST_ITE8152 */
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#endif /* __ASM_MACH_IRQS_H */
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