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ec58ba16e1
In case of HSDK we have intermediate INTC in for of DW APB GPIO controller which is used as a de-bounce logic for interrupt wires that come from outside the board. We cannot use existing "irq-dw-apb-ictl" driver here because all input lines are routed to corresponding output lines but not muxed into one line (this is configured in RTL and we cannot change this in software). But even if we add such a feature to "irq-dw-apb-ictl" driver that won't benefit us as higher-level INTC (in case of HSDK it is IDU) anyways has per-input control so adding fully-controller intermediate INTC will only bring some overhead on interrupt processing but no other benefits. Thus we just do one-time configuration of DW APB GPIO controller and forget about it. Based on implementation available on arch/arc/plat-axs10x/axs10x.c file. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
139 lines
4.5 KiB
C
139 lines
4.5 KiB
C
/*
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* ARC HSDK Platform support code
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*
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* Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/arcregs.h>
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#include <asm/io.h>
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#include <asm/mach_desc.h>
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#define ARC_CCM_UNUSED_ADDR 0x60000000
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static void __init hsdk_init_per_cpu(unsigned int cpu)
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{
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/*
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* By default ICCM is mapped to 0x7z while this area is used for
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* kernel virtual mappings, so move it to currently unused area.
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*/
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if (cpuinfo_arc700[cpu].iccm.sz)
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write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
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/*
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* By default DCCM is mapped to 0x8z while this area is used by kernel,
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* so move it to currently unused area.
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*/
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if (cpuinfo_arc700[cpu].dccm.sz)
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write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
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}
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#define ARC_PERIPHERAL_BASE 0xf0000000
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#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
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#define CREG_PAE (CREG_BASE + 0x180)
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#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
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#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
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#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
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#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
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#define HSDK_GPIO_INTC (ARC_PERIPHERAL_BASE + 0x3000)
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static void __init hsdk_enable_gpio_intc_wire(void)
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{
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/*
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* Peripherals on CPU Card are wired to cpu intc via intermediate
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* DW APB GPIO blocks (mainly for debouncing)
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*
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* ---------------------
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* | snps,archs-intc |
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* ---------------------
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* |
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* ----------------------
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* | snps,archs-idu-intc |
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* ----------------------
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* | | | | |
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* | [eth] [USB] [... other peripherals]
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* |
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* -------------------
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* | snps,dw-apb-intc |
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* -------------------
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* | | | |
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* [Bt] [HAPS] [... other peripherals]
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*
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* Current implementation of "irq-dw-apb-ictl" driver doesn't work well
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* with stacked INTCs. In particular problem happens if its master INTC
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* not yet instantiated. See discussion here -
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* https://lkml.org/lkml/2015/3/4/755
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*
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* So setup the first gpio block as a passive pass thru and hide it from
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* DT hardware topology - connect intc directly to cpu intc
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* The GPIO "wire" needs to be init nevertheless (here)
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*
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* One side adv is that peripheral interrupt handling avoids one nested
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* intc ISR hop
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*
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* According to HSDK User's Manual [1], "Table 2 Interrupt Mapping"
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* we have the following GPIO input lines used as sources of interrupt:
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* - GPIO[0] - Bluetooth interrupt of RS9113 module
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* - GPIO[2] - HAPS interrupt (on HapsTrak 3 connector)
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* - GPIO[3] - Audio codec (MAX9880A) interrupt
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* - GPIO[8-23] - Available on Arduino and PMOD_x headers
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* For now there's no use of Arduino and PMOD_x headers in Linux
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* use-case so we only enable lines 0, 2 and 3.
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*
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* [1] https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf
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*/
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#define GPIO_INTEN (HSDK_GPIO_INTC + 0x30)
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#define GPIO_INTMASK (HSDK_GPIO_INTC + 0x34)
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#define GPIO_INTTYPE_LEVEL (HSDK_GPIO_INTC + 0x38)
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#define GPIO_INT_POLARITY (HSDK_GPIO_INTC + 0x3c)
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#define GPIO_INT_CONNECTED_MASK 0x0d
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iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);
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iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK);
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iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);
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iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);
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iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
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}
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static void __init hsdk_init_early(void)
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{
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/*
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* PAE remapping for DMA clients does not work due to an RTL bug, so
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* CREG_PAE register must be programmed to all zeroes, otherwise it
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* will cause problems with DMA to/from peripherals even if PAE40 is
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* not used.
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*/
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/* Default is 1, which means "PAE offset = 4GByte" */
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writel_relaxed(0, (void __iomem *) CREG_PAE);
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/* Really apply settings made above */
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writel(1, (void __iomem *) CREG_PAE_UPDATE);
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/*
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* Switch SDIO external ciu clock divider from default div-by-8 to
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* minimum possible div-by-2.
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*/
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iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
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hsdk_enable_gpio_intc_wire();
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}
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static const char *hsdk_compat[] __initconst = {
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"snps,hsdk",
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NULL,
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};
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MACHINE_START(SIMULATION, "hsdk")
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.dt_compat = hsdk_compat,
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.init_early = hsdk_init_early,
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.init_per_cpu = hsdk_init_per_cpu,
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MACHINE_END
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