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a6867836db
Some Exynos boards have a separate regulator controlling a Boost 5V supply which goes as input for VBUS regulator. So adding a control for the same in driver, to enable vbus supply on the port. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
773 lines
20 KiB
C
773 lines
20 KiB
C
/*
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* Samsung EXYNOS5 SoC series USB DRD PHY driver
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*
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* Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
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*
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* Copyright (C) 2014 Samsung Electronics Co., Ltd.
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* Author: Vivek Gautam <gautam.vivek@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/mutex.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/exynos5-pmu.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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/* Exynos USB PHY registers */
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#define EXYNOS5_FSEL_9MHZ6 0x0
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#define EXYNOS5_FSEL_10MHZ 0x1
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#define EXYNOS5_FSEL_12MHZ 0x2
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#define EXYNOS5_FSEL_19MHZ2 0x3
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#define EXYNOS5_FSEL_20MHZ 0x4
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#define EXYNOS5_FSEL_24MHZ 0x5
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#define EXYNOS5_FSEL_50MHZ 0x7
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/* EXYNOS5: USB 3.0 DRD PHY registers */
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#define EXYNOS5_DRD_LINKSYSTEM 0x04
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#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
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#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
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#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
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#define EXYNOS5_DRD_PHYUTMI 0x08
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#define PHYUTMI_OTGDISABLE BIT(6)
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#define PHYUTMI_FORCESUSPEND BIT(1)
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#define PHYUTMI_FORCESLEEP BIT(0)
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#define EXYNOS5_DRD_PHYPIPE 0x0c
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#define EXYNOS5_DRD_PHYCLKRST 0x10
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#define PHYCLKRST_EN_UTMISUSPEND BIT(31)
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#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
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#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
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#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
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#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
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#define PHYCLKRST_SSC_EN BIT(20)
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#define PHYCLKRST_REF_SSP_EN BIT(19)
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#define PHYCLKRST_REF_CLKDIV2 BIT(18)
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#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
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#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
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#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
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#define PHYCLKRST_FSEL(_x) ((_x) << 5)
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#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
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#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
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#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
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#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
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#define PHYCLKRST_RETENABLEN BIT(4)
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#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
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#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
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#define PHYCLKRST_PORTRESET BIT(1)
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#define PHYCLKRST_COMMONONN BIT(0)
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#define EXYNOS5_DRD_PHYREG0 0x14
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#define EXYNOS5_DRD_PHYREG1 0x18
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#define EXYNOS5_DRD_PHYPARAM0 0x1c
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#define PHYPARAM0_REF_USE_PAD BIT(31)
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#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
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#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
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#define EXYNOS5_DRD_PHYPARAM1 0x20
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#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
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#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
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#define EXYNOS5_DRD_PHYTERM 0x24
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#define EXYNOS5_DRD_PHYTEST 0x28
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#define PHYTEST_POWERDOWN_SSP BIT(3)
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#define PHYTEST_POWERDOWN_HSP BIT(2)
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#define EXYNOS5_DRD_PHYADP 0x2c
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#define EXYNOS5_DRD_PHYUTMICLKSEL 0x30
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#define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2)
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#define EXYNOS5_DRD_PHYRESUME 0x34
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#define EXYNOS5_DRD_LINKPORT 0x44
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#define KHZ 1000
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#define MHZ (KHZ * KHZ)
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enum exynos5_usbdrd_phy_id {
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EXYNOS5_DRDPHY_UTMI,
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EXYNOS5_DRDPHY_PIPE3,
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EXYNOS5_DRDPHYS_NUM,
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};
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struct phy_usb_instance;
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struct exynos5_usbdrd_phy;
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struct exynos5_usbdrd_phy_config {
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u32 id;
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void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
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void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
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unsigned int (*set_refclk)(struct phy_usb_instance *inst);
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};
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struct exynos5_usbdrd_phy_drvdata {
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const struct exynos5_usbdrd_phy_config *phy_cfg;
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u32 pmu_offset_usbdrd0_phy;
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u32 pmu_offset_usbdrd1_phy;
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bool has_common_clk_gate;
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};
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/**
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* struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
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* @dev: pointer to device instance of this platform device
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* @reg_phy: usb phy controller register memory base
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* @clk: phy clock for register access
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* @pipeclk: clock for pipe3 phy
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* @utmiclk: clock for utmi+ phy
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* @itpclk: clock for ITP generation
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* @drv_data: pointer to SoC level driver data structure
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* @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
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* instances each with its 'phy' and 'phy_cfg'.
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* @extrefclk: frequency select settings when using 'separate
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* reference clocks' for SS and HS operations
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* @ref_clk: reference clock to PHY block from which PHY's
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* operational clocks are derived
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* vbus: VBUS regulator for phy
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* vbus_boost: Boost regulator for VBUS present on few Exynos boards
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*/
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struct exynos5_usbdrd_phy {
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struct device *dev;
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void __iomem *reg_phy;
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struct clk *clk;
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struct clk *pipeclk;
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struct clk *utmiclk;
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struct clk *itpclk;
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const struct exynos5_usbdrd_phy_drvdata *drv_data;
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struct phy_usb_instance {
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struct phy *phy;
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u32 index;
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struct regmap *reg_pmu;
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u32 pmu_offset;
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const struct exynos5_usbdrd_phy_config *phy_cfg;
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} phys[EXYNOS5_DRDPHYS_NUM];
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u32 extrefclk;
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struct clk *ref_clk;
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struct regulator *vbus;
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struct regulator *vbus_boost;
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};
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static inline
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struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst)
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{
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return container_of((inst), struct exynos5_usbdrd_phy,
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phys[(inst)->index]);
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}
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/*
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* exynos5_rate_to_clk() converts the supplied clock rate to the value that
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* can be written to the phy register.
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*/
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static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg)
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{
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/* EXYNOS5_FSEL_MASK */
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switch (rate) {
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case 9600 * KHZ:
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*reg = EXYNOS5_FSEL_9MHZ6;
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break;
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case 10 * MHZ:
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*reg = EXYNOS5_FSEL_10MHZ;
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break;
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case 12 * MHZ:
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*reg = EXYNOS5_FSEL_12MHZ;
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break;
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case 19200 * KHZ:
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*reg = EXYNOS5_FSEL_19MHZ2;
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break;
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case 20 * MHZ:
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*reg = EXYNOS5_FSEL_20MHZ;
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break;
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case 24 * MHZ:
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*reg = EXYNOS5_FSEL_24MHZ;
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break;
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case 50 * MHZ:
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*reg = EXYNOS5_FSEL_50MHZ;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
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unsigned int on)
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{
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unsigned int val;
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if (!inst->reg_pmu)
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return;
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val = on ? 0 : EXYNOS5_PHY_ENABLE;
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regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
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EXYNOS5_PHY_ENABLE, val);
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}
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/*
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* Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock
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* from clock core. Further sets multiplier values and spread spectrum
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* clock settings for SuperSpeed operations.
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*/
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static unsigned int
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exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
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{
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static u32 reg;
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struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
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/* restore any previous reference clock settings */
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
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/* Use EXTREFCLK as ref clock */
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reg &= ~PHYCLKRST_REFCLKSEL_MASK;
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reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
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/* FSEL settings corresponding to reference clock */
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reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
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PHYCLKRST_MPLL_MULTIPLIER_MASK |
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PHYCLKRST_SSC_REFCLKSEL_MASK;
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switch (phy_drd->extrefclk) {
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case EXYNOS5_FSEL_50MHZ:
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x00));
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break;
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case EXYNOS5_FSEL_24MHZ:
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x88));
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break;
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case EXYNOS5_FSEL_20MHZ:
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x00));
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break;
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case EXYNOS5_FSEL_19MHZ2:
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x88));
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break;
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default:
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dev_dbg(phy_drd->dev, "unsupported ref clk\n");
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break;
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}
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return reg;
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}
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/*
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* Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock
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* from clock core. Further sets the FSEL values for HighSpeed operations.
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*/
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static unsigned int
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exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
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{
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static u32 reg;
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struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
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/* restore any previous reference clock settings */
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
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reg &= ~PHYCLKRST_REFCLKSEL_MASK;
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reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
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reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
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PHYCLKRST_MPLL_MULTIPLIER_MASK |
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PHYCLKRST_SSC_REFCLKSEL_MASK;
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reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
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return reg;
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}
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static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
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{
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u32 reg;
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
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/* Set Tx De-Emphasis level */
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reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
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reg |= PHYPARAM1_PCS_TXDEEMPH;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
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reg &= ~PHYTEST_POWERDOWN_SSP;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
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}
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static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
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{
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u32 reg;
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
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/* Set Loss-of-Signal Detector sensitivity */
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reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
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reg |= PHYPARAM0_REF_LOSLEVEL;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
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/* Set Tx De-Emphasis level */
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reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
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reg |= PHYPARAM1_PCS_TXDEEMPH;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
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/* UTMI Power Control */
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writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
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reg &= ~PHYTEST_POWERDOWN_HSP;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
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}
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static int exynos5_usbdrd_phy_init(struct phy *phy)
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{
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int ret;
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u32 reg;
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struct phy_usb_instance *inst = phy_get_drvdata(phy);
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struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
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ret = clk_prepare_enable(phy_drd->clk);
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if (ret)
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return ret;
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/* Reset USB 3.0 PHY */
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writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
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writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
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/*
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* Setting the Frame length Adj value[6:1] to default 0x20
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* See xHCI 1.0 spec, 5.2.4
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*/
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reg = LINKSYSTEM_XHCI_VERSION_CONTROL |
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LINKSYSTEM_FLADJ(0x20);
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
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/* Select PHY CLK source */
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reg &= ~PHYPARAM0_REF_USE_PAD;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
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/* This bit must be set for both HS and SS operations */
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
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reg |= PHYUTMICLKSEL_UTMI_CLKSEL;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
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/* UTMI or PIPE3 specific init */
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inst->phy_cfg->phy_init(phy_drd);
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/* reference clock settings */
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reg = inst->phy_cfg->set_refclk(inst);
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/* Digital power supply in normal operating mode */
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reg |= PHYCLKRST_RETENABLEN |
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/* Enable ref clock for SS function */
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PHYCLKRST_REF_SSP_EN |
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/* Enable spread spectrum */
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PHYCLKRST_SSC_EN |
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/* Power down HS Bias and PLL blocks in suspend mode */
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PHYCLKRST_COMMONONN |
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/* Reset the port */
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PHYCLKRST_PORTRESET;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
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udelay(10);
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reg &= ~PHYCLKRST_PORTRESET;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
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clk_disable_unprepare(phy_drd->clk);
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return 0;
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}
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static int exynos5_usbdrd_phy_exit(struct phy *phy)
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{
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int ret;
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u32 reg;
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struct phy_usb_instance *inst = phy_get_drvdata(phy);
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struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
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ret = clk_prepare_enable(phy_drd->clk);
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if (ret)
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return ret;
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reg = PHYUTMI_OTGDISABLE |
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PHYUTMI_FORCESUSPEND |
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PHYUTMI_FORCESLEEP;
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
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/* Resetting the PHYCLKRST enable bits to reduce leakage current */
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
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reg &= ~(PHYCLKRST_REF_SSP_EN |
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PHYCLKRST_SSC_EN |
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PHYCLKRST_COMMONONN);
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writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
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/* Control PHYTEST to remove leakage current */
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reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
|
|
reg |= PHYTEST_POWERDOWN_SSP |
|
|
PHYTEST_POWERDOWN_HSP;
|
|
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
|
|
|
|
clk_disable_unprepare(phy_drd->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos5_usbdrd_phy_power_on(struct phy *phy)
|
|
{
|
|
int ret;
|
|
struct phy_usb_instance *inst = phy_get_drvdata(phy);
|
|
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
|
|
|
dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
|
|
|
|
clk_prepare_enable(phy_drd->ref_clk);
|
|
if (!phy_drd->drv_data->has_common_clk_gate) {
|
|
clk_prepare_enable(phy_drd->pipeclk);
|
|
clk_prepare_enable(phy_drd->utmiclk);
|
|
clk_prepare_enable(phy_drd->itpclk);
|
|
}
|
|
|
|
/* Enable VBUS supply */
|
|
if (phy_drd->vbus_boost) {
|
|
ret = regulator_enable(phy_drd->vbus_boost);
|
|
if (ret) {
|
|
dev_err(phy_drd->dev,
|
|
"Failed to enable VBUS boost supply\n");
|
|
goto fail_vbus;
|
|
}
|
|
}
|
|
|
|
if (phy_drd->vbus) {
|
|
ret = regulator_enable(phy_drd->vbus);
|
|
if (ret) {
|
|
dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
|
|
goto fail_vbus_boost;
|
|
}
|
|
}
|
|
|
|
/* Power-on PHY*/
|
|
inst->phy_cfg->phy_isol(inst, 0);
|
|
|
|
return 0;
|
|
|
|
fail_vbus_boost:
|
|
if (phy_drd->vbus_boost)
|
|
regulator_disable(phy_drd->vbus_boost);
|
|
|
|
fail_vbus:
|
|
clk_disable_unprepare(phy_drd->ref_clk);
|
|
if (!phy_drd->drv_data->has_common_clk_gate) {
|
|
clk_disable_unprepare(phy_drd->itpclk);
|
|
clk_disable_unprepare(phy_drd->utmiclk);
|
|
clk_disable_unprepare(phy_drd->pipeclk);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int exynos5_usbdrd_phy_power_off(struct phy *phy)
|
|
{
|
|
struct phy_usb_instance *inst = phy_get_drvdata(phy);
|
|
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
|
|
|
dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
|
|
|
|
/* Power-off the PHY */
|
|
inst->phy_cfg->phy_isol(inst, 1);
|
|
|
|
/* Disable VBUS supply */
|
|
if (phy_drd->vbus)
|
|
regulator_disable(phy_drd->vbus);
|
|
if (phy_drd->vbus_boost)
|
|
regulator_disable(phy_drd->vbus_boost);
|
|
|
|
clk_disable_unprepare(phy_drd->ref_clk);
|
|
if (!phy_drd->drv_data->has_common_clk_gate) {
|
|
clk_disable_unprepare(phy_drd->itpclk);
|
|
clk_disable_unprepare(phy_drd->pipeclk);
|
|
clk_disable_unprepare(phy_drd->utmiclk);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
|
|
struct of_phandle_args *args)
|
|
{
|
|
struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
|
|
|
|
if (WARN_ON(args->args[0] > EXYNOS5_DRDPHYS_NUM))
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
return phy_drd->phys[args->args[0]].phy;
|
|
}
|
|
|
|
static struct phy_ops exynos5_usbdrd_phy_ops = {
|
|
.init = exynos5_usbdrd_phy_init,
|
|
.exit = exynos5_usbdrd_phy_exit,
|
|
.power_on = exynos5_usbdrd_phy_power_on,
|
|
.power_off = exynos5_usbdrd_phy_power_off,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
|
|
{
|
|
unsigned long ref_rate;
|
|
int ret;
|
|
|
|
phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
|
|
if (IS_ERR(phy_drd->clk)) {
|
|
dev_err(phy_drd->dev, "Failed to get phy clock\n");
|
|
return PTR_ERR(phy_drd->clk);
|
|
}
|
|
|
|
phy_drd->ref_clk = devm_clk_get(phy_drd->dev, "ref");
|
|
if (IS_ERR(phy_drd->ref_clk)) {
|
|
dev_err(phy_drd->dev, "Failed to get phy reference clock\n");
|
|
return PTR_ERR(phy_drd->ref_clk);
|
|
}
|
|
ref_rate = clk_get_rate(phy_drd->ref_clk);
|
|
|
|
ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
|
|
if (ret) {
|
|
dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
|
|
ref_rate);
|
|
return ret;
|
|
}
|
|
|
|
if (!phy_drd->drv_data->has_common_clk_gate) {
|
|
phy_drd->pipeclk = devm_clk_get(phy_drd->dev, "phy_pipe");
|
|
if (IS_ERR(phy_drd->pipeclk)) {
|
|
dev_info(phy_drd->dev,
|
|
"PIPE3 phy operational clock not specified\n");
|
|
phy_drd->pipeclk = NULL;
|
|
}
|
|
|
|
phy_drd->utmiclk = devm_clk_get(phy_drd->dev, "phy_utmi");
|
|
if (IS_ERR(phy_drd->utmiclk)) {
|
|
dev_info(phy_drd->dev,
|
|
"UTMI phy operational clock not specified\n");
|
|
phy_drd->utmiclk = NULL;
|
|
}
|
|
|
|
phy_drd->itpclk = devm_clk_get(phy_drd->dev, "itp");
|
|
if (IS_ERR(phy_drd->itpclk)) {
|
|
dev_info(phy_drd->dev,
|
|
"ITP clock from main OSC not specified\n");
|
|
phy_drd->itpclk = NULL;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
|
|
{
|
|
.id = EXYNOS5_DRDPHY_UTMI,
|
|
.phy_isol = exynos5_usbdrd_phy_isol,
|
|
.phy_init = exynos5_usbdrd_utmi_init,
|
|
.set_refclk = exynos5_usbdrd_utmi_set_refclk,
|
|
},
|
|
{
|
|
.id = EXYNOS5_DRDPHY_PIPE3,
|
|
.phy_isol = exynos5_usbdrd_phy_isol,
|
|
.phy_init = exynos5_usbdrd_pipe3_init,
|
|
.set_refclk = exynos5_usbdrd_pipe3_set_refclk,
|
|
},
|
|
};
|
|
|
|
static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
|
|
.phy_cfg = phy_cfg_exynos5,
|
|
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
|
|
.pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
|
|
.has_common_clk_gate = true,
|
|
};
|
|
|
|
static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
|
|
.phy_cfg = phy_cfg_exynos5,
|
|
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
|
|
.has_common_clk_gate = true,
|
|
};
|
|
|
|
static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
|
|
.phy_cfg = phy_cfg_exynos5,
|
|
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
|
|
.has_common_clk_gate = false,
|
|
};
|
|
|
|
static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
|
|
{
|
|
.compatible = "samsung,exynos5250-usbdrd-phy",
|
|
.data = &exynos5250_usbdrd_phy
|
|
}, {
|
|
.compatible = "samsung,exynos5420-usbdrd-phy",
|
|
.data = &exynos5420_usbdrd_phy
|
|
}, {
|
|
.compatible = "samsung,exynos7-usbdrd-phy",
|
|
.data = &exynos7_usbdrd_phy
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, exynos5_usbdrd_phy_of_match);
|
|
|
|
static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct exynos5_usbdrd_phy *phy_drd;
|
|
struct phy_provider *phy_provider;
|
|
struct resource *res;
|
|
const struct of_device_id *match;
|
|
const struct exynos5_usbdrd_phy_drvdata *drv_data;
|
|
struct regmap *reg_pmu;
|
|
u32 pmu_offset;
|
|
int i, ret;
|
|
int channel;
|
|
|
|
phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
|
|
if (!phy_drd)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(dev, phy_drd);
|
|
phy_drd->dev = dev;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
phy_drd->reg_phy = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(phy_drd->reg_phy))
|
|
return PTR_ERR(phy_drd->reg_phy);
|
|
|
|
match = of_match_node(exynos5_usbdrd_phy_of_match, pdev->dev.of_node);
|
|
|
|
drv_data = match->data;
|
|
phy_drd->drv_data = drv_data;
|
|
|
|
ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
|
|
"samsung,pmu-syscon");
|
|
if (IS_ERR(reg_pmu)) {
|
|
dev_err(dev, "Failed to lookup PMU regmap\n");
|
|
return PTR_ERR(reg_pmu);
|
|
}
|
|
|
|
/*
|
|
* Exynos5420 SoC has multiple channels for USB 3.0 PHY, with
|
|
* each having separate power control registers.
|
|
* 'channel' facilitates to set such registers.
|
|
*/
|
|
channel = of_alias_get_id(node, "usbdrdphy");
|
|
if (channel < 0)
|
|
dev_dbg(dev, "Not a multi-controller usbdrd phy\n");
|
|
|
|
switch (channel) {
|
|
case 1:
|
|
pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy;
|
|
break;
|
|
case 0:
|
|
default:
|
|
pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy;
|
|
break;
|
|
}
|
|
|
|
/* Get Vbus regulators */
|
|
phy_drd->vbus = devm_regulator_get(dev, "vbus");
|
|
if (IS_ERR(phy_drd->vbus)) {
|
|
ret = PTR_ERR(phy_drd->vbus);
|
|
if (ret == -EPROBE_DEFER)
|
|
return ret;
|
|
|
|
dev_warn(dev, "Failed to get VBUS supply regulator\n");
|
|
phy_drd->vbus = NULL;
|
|
}
|
|
|
|
phy_drd->vbus_boost = devm_regulator_get(dev, "vbus-boost");
|
|
if (IS_ERR(phy_drd->vbus_boost)) {
|
|
ret = PTR_ERR(phy_drd->vbus_boost);
|
|
if (ret == -EPROBE_DEFER)
|
|
return ret;
|
|
|
|
dev_warn(dev, "Failed to get VBUS boost supply regulator\n");
|
|
phy_drd->vbus_boost = NULL;
|
|
}
|
|
|
|
dev_vdbg(dev, "Creating usbdrd_phy phy\n");
|
|
|
|
for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
|
|
struct phy *phy = devm_phy_create(dev, NULL,
|
|
&exynos5_usbdrd_phy_ops);
|
|
if (IS_ERR(phy)) {
|
|
dev_err(dev, "Failed to create usbdrd_phy phy\n");
|
|
return PTR_ERR(phy);
|
|
}
|
|
|
|
phy_drd->phys[i].phy = phy;
|
|
phy_drd->phys[i].index = i;
|
|
phy_drd->phys[i].reg_pmu = reg_pmu;
|
|
phy_drd->phys[i].pmu_offset = pmu_offset;
|
|
phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
|
|
phy_set_drvdata(phy, &phy_drd->phys[i]);
|
|
}
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev,
|
|
exynos5_usbdrd_phy_xlate);
|
|
if (IS_ERR(phy_provider)) {
|
|
dev_err(phy_drd->dev, "Failed to register phy provider\n");
|
|
return PTR_ERR(phy_provider);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver exynos5_usb3drd_phy = {
|
|
.probe = exynos5_usbdrd_phy_probe,
|
|
.driver = {
|
|
.of_match_table = exynos5_usbdrd_phy_of_match,
|
|
.name = "exynos5_usb3drd_phy",
|
|
}
|
|
};
|
|
|
|
module_platform_driver(exynos5_usb3drd_phy);
|
|
MODULE_DESCRIPTION("Samsung EXYNOS5 SoCs USB 3.0 DRD controller PHY driver");
|
|
MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:exynos5_usb3drd_phy");
|