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When using an rbtree cache, there can be allocations the first time a register is accessed. This can cause an attempt to schedule while atomic in the case that the regmap is using a spinlock. This could be fixed by either initializing all the registers or using a flat cache. The register maps for tegra30_ahub and tegra30_i2s are dense and don't save much from using a tree so convert them to flat. Tegra30 changes tested on Norrin, Tegra20 changes compile. Signed-off-by: Dylan Reid <dgreid@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| tegra20_ac97.c | ||
| tegra20_ac97.h | ||
| tegra20_das.c | ||
| tegra20_das.h | ||
| tegra20_i2s.c | ||
| tegra20_i2s.h | ||
| tegra20_spdif.c | ||
| tegra20_spdif.h | ||
| tegra30_ahub.c | ||
| tegra30_ahub.h | ||
| tegra30_i2s.c | ||
| tegra30_i2s.h | ||
| tegra_alc5632.c | ||
| tegra_asoc_utils.c | ||
| tegra_asoc_utils.h | ||
| tegra_max98090.c | ||
| tegra_pcm.c | ||
| tegra_pcm.h | ||
| tegra_rt5640.c | ||
| tegra_wm8753.c | ||
| tegra_wm8903.c | ||
| tegra_wm9712.c | ||
| trimslice.c | ||