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883aebf6e1
sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS
registers of QMP PHY v5.20. So use the v5.20 specific register names.
Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to
PCS_EQ_CONFIG{4/5}.
Fixes: 2c91bf6bf2 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
15 lines
333 B
C
15 lines
333 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022, Linaro Ltd.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V5_20_H_
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#define QCOM_PHY_QMP_PCS_V5_20_H_
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#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
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#define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
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#define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4
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#endif
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