mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-11 21:38:32 +08:00
3c9ee7ef87
- remove __{,test_and_}{set,clear,change}_bit() and test_bit()
- unless defined(CONFIG_CPU_MIPS32) or defined(CONFIG_CPU_MIPS64)
- remove __ffs()
- remove ffs()
- remove ffz()
- remove fls()
- remove fls64()
- remove find_{next,first}{,_zero}_bit()
- remove sched_find_first_bit()
- remove generic_hweight64()
- remove generic_hweight{32,16,8}()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove ext2_{set,clear}_bit_atomic()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
541 lines
13 KiB
C
541 lines
13 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org)
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* Copyright (c) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_BITOPS_H
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#define _ASM_BITOPS_H
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#include <linux/config.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/bug.h>
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#include <asm/byteorder.h> /* sigh ... */
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#include <asm/cpu-features.h>
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#if (_MIPS_SZLONG == 32)
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#define SZLONG_LOG 5
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#define SZLONG_MASK 31UL
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#define __LL "ll "
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#define __SC "sc "
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#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
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#elif (_MIPS_SZLONG == 64)
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#define SZLONG_LOG 6
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#define SZLONG_MASK 63UL
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#define __LL "lld "
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#define __SC "scd "
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#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
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#endif
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#ifdef __KERNEL__
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#include <asm/interrupt.h>
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#include <asm/sgidefs.h>
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#include <asm/war.h>
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() smp_mb()
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/*
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* Only disable interrupt for kernel mode stuff to keep usermode stuff
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* that dares to use kernel include files alive.
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*/
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#define __bi_flags unsigned long flags
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#define __bi_local_irq_save(x) local_irq_save(x)
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#define __bi_local_irq_restore(x) local_irq_restore(x)
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#else
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#define __bi_flags
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#define __bi_local_irq_save(x)
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#define __bi_local_irq_restore(x)
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#endif /* __KERNEL__ */
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/*
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # set_bit \n"
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" or %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # set_bit \n"
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" or %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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*a |= mask;
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__bi_local_irq_restore(flags);
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}
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}
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/*
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # clear_bit \n"
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" and %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # clear_bit \n"
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" and %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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*a &= ~mask;
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__bi_local_irq_restore(flags);
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}
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}
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/*
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # change_bit \n"
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" xor %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # change_bit \n"
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" xor %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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*a ^= mask;
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__bi_local_irq_restore(flags);
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}
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}
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/*
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # test_and_set_bit \n"
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set mips3 \n"
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"1: " __LL "%0, %1 # test_and_set_bit \n"
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" beqz %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set pop \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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int retval;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a |= mask;
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__bi_local_irq_restore(flags);
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return retval;
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}
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}
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/*
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_clear_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # test_and_clear_bit \n"
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" or %2, %0, %3 \n"
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" xor %2, %3 \n"
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" " __SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" .set mips3 \n"
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"1: " __LL "%0, %1 # test_and_clear_bit \n"
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" or %2, %0, %3 \n"
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" xor %2, %3 \n"
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" " __SC "%2, %1 \n"
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" beqz %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set pop \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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int retval;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a &= ~mask;
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__bi_local_irq_restore(flags);
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return retval;
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}
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}
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/*
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_change_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: " __LL "%0, %1 # test_and_change_bit \n"
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" xor %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
|
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|
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
|
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" .set mips3 \n"
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"1: " __LL "%0, %1 # test_and_change_bit \n"
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" xor %2, %0, %3 \n"
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" " __SC "\t%2, %1 \n"
|
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" beqz %2, 1b \n"
|
|
" and %2, %0, %3 \n"
|
|
#ifdef CONFIG_SMP
|
|
" sync \n"
|
|
#endif
|
|
" .set pop \n"
|
|
: "=&r" (temp), "=m" (*m), "=&r" (res)
|
|
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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|
|
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return res != 0;
|
|
} else {
|
|
volatile unsigned long *a = addr;
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|
unsigned long mask, retval;
|
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__bi_flags;
|
|
|
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a += nr >> SZLONG_LOG;
|
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mask = 1UL << (nr & SZLONG_MASK);
|
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__bi_local_irq_save(flags);
|
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retval = (mask & *a) != 0;
|
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*a ^= mask;
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__bi_local_irq_restore(flags);
|
|
|
|
return retval;
|
|
}
|
|
}
|
|
|
|
#undef __bi_flags
|
|
#undef __bi_local_irq_save
|
|
#undef __bi_local_irq_restore
|
|
|
|
#include <asm-generic/bitops/non-atomic.h>
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|
|
|
/*
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|
* Return the bit position (0..63) of the most significant 1 bit in a word
|
|
* Returns -1 if no 1 bit exists
|
|
*/
|
|
static inline int __ilog2(unsigned long x)
|
|
{
|
|
int lz;
|
|
|
|
if (sizeof(x) == 4) {
|
|
__asm__ (
|
|
" .set push \n"
|
|
" .set mips32 \n"
|
|
" clz %0, %1 \n"
|
|
" .set pop \n"
|
|
: "=r" (lz)
|
|
: "r" (x));
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|
|
|
return 31 - lz;
|
|
}
|
|
|
|
BUG_ON(sizeof(x) != 8);
|
|
|
|
__asm__ (
|
|
" .set push \n"
|
|
" .set mips64 \n"
|
|
" dclz %0, %1 \n"
|
|
" .set pop \n"
|
|
: "=r" (lz)
|
|
: "r" (x));
|
|
|
|
return 63 - lz;
|
|
}
|
|
|
|
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
|
|
|
|
/*
|
|
* __ffs - find first bit in word.
|
|
* @word: The word to search
|
|
*
|
|
* Returns 0..SZLONG-1
|
|
* Undefined if no bit exists, so code should check against 0 first.
|
|
*/
|
|
static inline unsigned long __ffs(unsigned long word)
|
|
{
|
|
return __ilog2(word & -word);
|
|
}
|
|
|
|
/*
|
|
* ffs - find first bit set.
|
|
* @word: The word to search
|
|
*
|
|
* Returns 1..SZLONG
|
|
* Returns 0 if no bit exists
|
|
*/
|
|
|
|
static inline unsigned long ffs(unsigned long word)
|
|
{
|
|
if (!word)
|
|
return 0;
|
|
|
|
return __ffs(word) + 1;
|
|
}
|
|
|
|
/*
|
|
* ffz - find first zero in word.
|
|
* @word: The word to search
|
|
*
|
|
* Undefined if no zero exists, so code should check against ~0UL first.
|
|
*/
|
|
static inline unsigned long ffz(unsigned long word)
|
|
{
|
|
return __ffs (~word);
|
|
}
|
|
|
|
/*
|
|
* fls - find last bit set.
|
|
* @word: The word to search
|
|
*
|
|
* Returns 1..SZLONG
|
|
* Returns 0 if no bit exists
|
|
*/
|
|
static inline unsigned long fls(unsigned long word)
|
|
{
|
|
#ifdef CONFIG_CPU_MIPS32
|
|
__asm__ ("clz %0, %1" : "=r" (word) : "r" (word));
|
|
|
|
return 32 - word;
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_MIPS64
|
|
__asm__ ("dclz %0, %1" : "=r" (word) : "r" (word));
|
|
|
|
return 64 - word;
|
|
#endif
|
|
}
|
|
|
|
#else
|
|
|
|
#include <asm-generic/bitops/__ffs.h>
|
|
#include <asm-generic/bitops/ffs.h>
|
|
#include <asm-generic/bitops/ffz.h>
|
|
#include <asm-generic/bitops/fls.h>
|
|
|
|
#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
|
|
|
|
#include <asm-generic/bitops/fls64.h>
|
|
#include <asm-generic/bitops/find.h>
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
#include <asm-generic/bitops/sched.h>
|
|
#include <asm-generic/bitops/hweight.h>
|
|
#include <asm-generic/bitops/ext2-non-atomic.h>
|
|
#include <asm-generic/bitops/ext2-atomic.h>
|
|
#include <asm-generic/bitops/minix.h>
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* _ASM_BITOPS_H */
|