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58a8d9be52
Patch adds DT entries for clockgen A0 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
69 lines
1.4 KiB
Plaintext
69 lines
1.4 KiB
Plaintext
/*
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* Copyright (C) 2014 STMicroelectronics R&D Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: arm-periph-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <600000000>;
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};
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/*
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* Bootloader initialized system infrastructure clock for
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* serial devices.
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*/
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clk_ext2f_a9: clockgen-c0@13 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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clock-output-names = "clk-s-icn-reg-0";
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};
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clockgen-a@090ff000 {
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compatible = "st,clkgen-c32";
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reg = <0x90ff000 0x1000>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll-ofd-0";
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};
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen";
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#clock-cells = <1>;
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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clock-output-names = "clk-ic-lmi0";
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};
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};
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};
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};
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