Marek Vasut f7f9abc5ea phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED ... The 'fsl,refclk-pad-mode' DT property used to select clock source for PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first two options are handled correctly by the driver, the last one is not, this patch implements support for the last option. The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC internal PLL and output to PCIE_RESREF external IO pin. The last IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY clock are sourced from SoC internal PLL and not output anywhere. Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-arm-kernel@lists.infradead.org To: linux-phy@lists.infradead.org Link: https://lore.kernel.org/r/20220413140710.10074-1-marex@denx.de Signed-off-by: Vinod Koul <vkoul@kernel.org>		2022-04-20 14:45:55 +05:30
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Kconfig	phy: PHY_FSL_LYNX_28G should depend on ARCH_LAYERSCAPE	2022-03-29 08:45:16 -07:00
Makefile	phy: add support for the Layerscape SerDes 28G	2022-03-14 10:41:50 +00:00
phy-fsl-imx8-mipi-dphy.c	phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support	2022-04-20 12:59:50 +05:30
phy-fsl-imx8m-pcie.c	phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED	2022-04-20 14:45:55 +05:30
phy-fsl-imx8mq-usb.c	phy: freescale: convert to devm_platform_ioremap_resource	2020-11-16 12:47:46 +05:30
phy-fsl-lynx-28g.c	phy: Remove duplicated include in phy-fsl-lynx-28g.c	2022-03-16 19:34:34 -07:00