Swapnil Jakhade e72659b69f phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configuration ... This patch adds workaround for TI J721E errata i2183 (https://www.ti.com/lit/er/sprz455a/sprz455a.pdf). PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle. Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitance on the transmit lines to discharge. This causes subsequent receiver detection to always fail even if a receiver gets connected eventually. The workaround only works for 1-lane PCIe configuration. This workaround involves enabling receiver detect override by setting TX_RCVDET_OVRD_PREG_j register of the lane running PCIe to 0x2. This causes SERDES to indicate successful receiver detect when LTSSM is in Detect.Active state, whether a receiver is actually present or not. If the receiver is present, LTSSM proceeds to link up as expected. However if receiver is not present, LTSSM will time out in Polling.Configuration substate since the expected training sequence packets will not be received. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20220303055026.24899-1-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2022-04-13 15:26:54 +05:30
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cdns-dphy-rx.c	phy: cadence: Add Cadence D-PHY Rx driver	2022-03-02 19:54:42 +05:30
cdns-dphy.c	phy: cadence: convert to devm_platform_ioremap_resource	2020-11-16 12:47:46 +05:30
Kconfig	phy: cadence: Add Cadence D-PHY Rx driver	2022-03-02 19:54:42 +05:30
Makefile	phy: cadence: Add Cadence D-PHY Rx driver	2022-03-02 19:54:42 +05:30
phy-cadence-salvo.c	phy/cadence: Use of_device_get_match_data()	2022-02-25 13:58:12 +05:30
phy-cadence-sierra.c	phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configuration	2022-04-13 15:26:54 +05:30
phy-cadence-torrent.c	phy: cadence-torrent: use swap() to make code cleaner	2021-11-23 11:24:30 +05:30