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567e58cf96
There are 2 mmu cells in a M4U HW. we could adjust some larbs entering mmu0 or mmu1 to balance the bandwidth via the smi-common register SMI_BUS_SEL(0x220)(Each larb occupy 2 bits). In mt8183, For better performance, we switch larb1/2/5/7 to enter mmu1 while the others still keep enter mmu0. In mt8173 and mt2712, we don't get the performance issue, Keep its default value(0x0), that means all the larbs enter mmu0. Note: smi gen1(mt2701/mt7623) don't have this bus_sel. And, the base of smi-common is completely different with smi_ao_base of gen1, thus I add new variable for that. CC: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> |
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| .. | ||
| samsung | ||
| tegra | ||
| .gitignore | ||
| atmel-ebi.c | ||
| atmel-sdramc.c | ||
| brcmstb_dpfe.c | ||
| da8xx-ddrctl.c | ||
| emif-asm-offsets.c | ||
| emif.c | ||
| emif.h | ||
| fsl_ifc.c | ||
| fsl-corenet-cf.c | ||
| jedec_ddr_data.c | ||
| jedec_ddr.h | ||
| jz4780-nemc.c | ||
| Kconfig | ||
| Makefile | ||
| mtk-smi.c | ||
| mvebu-devbus.c | ||
| of_memory.c | ||
| of_memory.h | ||
| omap-gpmc.c | ||
| pl172.c | ||
| pl353-smc.c | ||
| ti-aemif.c | ||
| ti-emif-pm.c | ||
| ti-emif-sram-pm.S | ||