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a03d9f94cc
The max depth of a fastreg mr depends on whether the device supports DSGL or not. So compute it dynamically based on the device support and the module use_dsgl option. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
680 lines
18 KiB
C
680 lines
18 KiB
C
/*
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* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __T4_H__
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#define __T4_H__
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#include "t4_hw.h"
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#include "t4_regs.h"
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#include "t4_msg.h"
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#include "t4fw_ri_api.h"
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#define T4_MAX_NUM_QP 65536
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#define T4_MAX_NUM_CQ 65536
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#define T4_MAX_NUM_PD 65536
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#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
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#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
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#define T4_MAX_IQ_SIZE (65520 - 1)
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#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
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#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
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#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
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#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
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#define T4_MAX_NUM_STAG (1<<15)
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#define T4_MAX_MR_SIZE (~0ULL)
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#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
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#define T4_STAG_UNSET 0xffffffff
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#define T4_FW_MAJ 0
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#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
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#define A_PCIE_MA_SYNC 0x30b4
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struct t4_status_page {
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__be32 rsvd1; /* flit 0 - hw owns */
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__be16 rsvd2;
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__be16 qid;
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__be16 cidx;
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__be16 pidx;
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u8 qp_err; /* flit 1 - sw owns */
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u8 db_off;
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u8 pad;
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u16 host_wq_pidx;
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u16 host_cidx;
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u16 host_pidx;
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};
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#define T4_EQ_ENTRY_SIZE 64
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#define T4_SQ_NUM_SLOTS 5
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#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
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#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
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sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
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#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
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sizeof(struct fw_ri_immd)))
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#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
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sizeof(struct fw_ri_rdma_write_wr) - \
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sizeof(struct fw_ri_immd)))
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#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
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sizeof(struct fw_ri_rdma_write_wr) - \
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sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
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#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
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sizeof(struct fw_ri_immd)) & ~31UL)
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#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
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#define T4_MAX_FR_DSGL 1024
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#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
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static inline int t4_max_fr_depth(int use_dsgl)
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{
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return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
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}
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#define T4_RQ_NUM_SLOTS 2
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#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
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#define T4_MAX_RECV_SGE 4
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union t4_wr {
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struct fw_ri_res_wr res;
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struct fw_ri_wr ri;
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struct fw_ri_rdma_write_wr write;
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struct fw_ri_send_wr send;
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struct fw_ri_rdma_read_wr read;
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struct fw_ri_bind_mw_wr bind;
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struct fw_ri_fr_nsmr_wr fr;
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struct fw_ri_inv_lstag_wr inv;
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struct t4_status_page status;
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__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
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};
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union t4_recv_wr {
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struct fw_ri_recv_wr recv;
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struct t4_status_page status;
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__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
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};
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static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
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enum fw_wr_opcodes opcode, u8 flags, u8 len16)
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{
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wqe->send.opcode = (u8)opcode;
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wqe->send.flags = flags;
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wqe->send.wrid = wrid;
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wqe->send.r1[0] = 0;
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wqe->send.r1[1] = 0;
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wqe->send.r1[2] = 0;
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wqe->send.len16 = len16;
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}
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/* CQE/AE status codes */
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#define T4_ERR_SUCCESS 0x0
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#define T4_ERR_STAG 0x1 /* STAG invalid: either the */
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/* STAG is offlimt, being 0, */
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/* or STAG_key mismatch */
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#define T4_ERR_PDID 0x2 /* PDID mismatch */
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#define T4_ERR_QPID 0x3 /* QPID mismatch */
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#define T4_ERR_ACCESS 0x4 /* Invalid access right */
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#define T4_ERR_WRAP 0x5 /* Wrap error */
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#define T4_ERR_BOUND 0x6 /* base and bounds voilation */
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#define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
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/* shared memory region */
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#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
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/* shared memory region */
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#define T4_ERR_ECC 0x9 /* ECC error detected */
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#define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
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/* reading PSTAG for a MW */
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/* Invalidate */
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#define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
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/* software error */
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#define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
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#define T4_ERR_CRC 0x10 /* CRC error */
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#define T4_ERR_MARKER 0x11 /* Marker error */
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#define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
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#define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
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#define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
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#define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
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#define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
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#define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
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#define T4_ERR_MSN 0x18 /* MSN error */
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#define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
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#define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
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/* or READ_REQ */
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#define T4_ERR_MSN_GAP 0x1B
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#define T4_ERR_MSN_RANGE 0x1C
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#define T4_ERR_IRD_OVERFLOW 0x1D
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#define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
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/* software error */
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#define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
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/* mismatch) */
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/*
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* CQE defs
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*/
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struct t4_cqe {
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__be32 header;
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__be32 len;
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union {
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struct {
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__be32 stag;
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__be32 msn;
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} rcqe;
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struct {
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u32 nada1;
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u16 nada2;
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u16 cidx;
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} scqe;
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struct {
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__be32 wrid_hi;
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__be32 wrid_low;
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} gen;
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} u;
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__be64 reserved;
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__be64 bits_type_ts;
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};
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/* macros for flit 0 of the cqe */
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#define S_CQE_QPID 12
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#define M_CQE_QPID 0xFFFFF
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#define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
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#define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
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#define S_CQE_SWCQE 11
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#define M_CQE_SWCQE 0x1
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#define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
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#define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
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#define S_CQE_STATUS 5
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#define M_CQE_STATUS 0x1F
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#define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
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#define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
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#define S_CQE_TYPE 4
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#define M_CQE_TYPE 0x1
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#define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
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#define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
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#define S_CQE_OPCODE 0
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#define M_CQE_OPCODE 0xF
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#define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
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#define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
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#define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
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#define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
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#define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
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#define SQ_TYPE(x) (CQE_TYPE((x)))
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#define RQ_TYPE(x) (!CQE_TYPE((x)))
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#define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
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#define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
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#define CQE_SEND_OPCODE(x)( \
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(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
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(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
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(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
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(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
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#define CQE_LEN(x) (be32_to_cpu((x)->len))
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/* used for RQ completion processing */
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#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
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#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
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/* used for SQ completion processing */
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#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
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/* generic accessor macros */
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#define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi)
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#define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low)
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/* macros for flit 3 of the cqe */
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#define S_CQE_GENBIT 63
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#define M_CQE_GENBIT 0x1
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#define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
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#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
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#define S_CQE_OVFBIT 62
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#define M_CQE_OVFBIT 0x1
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#define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
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#define S_CQE_IQTYPE 60
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#define M_CQE_IQTYPE 0x3
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#define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
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#define M_CQE_TS 0x0fffffffffffffffULL
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#define G_CQE_TS(x) ((x) & M_CQE_TS)
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#define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
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#define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
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#define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
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struct t4_swsqe {
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u64 wr_id;
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struct t4_cqe cqe;
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int read_len;
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int opcode;
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int complete;
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int signaled;
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u16 idx;
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int flushed;
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};
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static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
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{
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#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
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return pgprot_writecombine(prot);
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#else
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return pgprot_noncached(prot);
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#endif
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}
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enum {
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T4_SQ_ONCHIP = (1<<0),
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};
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struct t4_sq {
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union t4_wr *queue;
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dma_addr_t dma_addr;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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unsigned long phys_addr;
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struct t4_swsqe *sw_sq;
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struct t4_swsqe *oldest_read;
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u64 __iomem *udb;
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size_t memsize;
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u32 qid;
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u16 in_use;
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u16 size;
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u16 cidx;
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u16 pidx;
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u16 wq_pidx;
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u16 wq_pidx_inc;
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u16 flags;
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short flush_cidx;
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};
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struct t4_swrqe {
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u64 wr_id;
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};
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struct t4_rq {
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union t4_recv_wr *queue;
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dma_addr_t dma_addr;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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struct t4_swrqe *sw_rq;
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u64 __iomem *udb;
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size_t memsize;
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u32 qid;
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u32 msn;
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u32 rqt_hwaddr;
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u16 rqt_size;
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u16 in_use;
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u16 size;
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u16 cidx;
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u16 pidx;
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u16 wq_pidx;
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u16 wq_pidx_inc;
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};
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struct t4_wq {
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struct t4_sq sq;
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struct t4_rq rq;
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void __iomem *db;
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void __iomem *gts;
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struct c4iw_rdev *rdev;
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int flushed;
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};
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static inline int t4_rqes_posted(struct t4_wq *wq)
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{
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return wq->rq.in_use;
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}
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static inline int t4_rq_empty(struct t4_wq *wq)
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{
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return wq->rq.in_use == 0;
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}
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static inline int t4_rq_full(struct t4_wq *wq)
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{
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return wq->rq.in_use == (wq->rq.size - 1);
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}
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static inline u32 t4_rq_avail(struct t4_wq *wq)
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{
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return wq->rq.size - 1 - wq->rq.in_use;
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}
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static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
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{
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wq->rq.in_use++;
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if (++wq->rq.pidx == wq->rq.size)
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wq->rq.pidx = 0;
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wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
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if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
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wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
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}
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static inline void t4_rq_consume(struct t4_wq *wq)
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{
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wq->rq.in_use--;
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wq->rq.msn++;
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if (++wq->rq.cidx == wq->rq.size)
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wq->rq.cidx = 0;
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}
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static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
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{
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return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
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}
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static inline u16 t4_rq_wq_size(struct t4_wq *wq)
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{
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return wq->rq.size * T4_RQ_NUM_SLOTS;
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}
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static inline int t4_sq_onchip(struct t4_sq *sq)
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{
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return sq->flags & T4_SQ_ONCHIP;
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}
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static inline int t4_sq_empty(struct t4_wq *wq)
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{
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return wq->sq.in_use == 0;
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}
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static inline int t4_sq_full(struct t4_wq *wq)
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{
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return wq->sq.in_use == (wq->sq.size - 1);
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}
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static inline u32 t4_sq_avail(struct t4_wq *wq)
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{
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return wq->sq.size - 1 - wq->sq.in_use;
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}
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static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
|
|
{
|
|
wq->sq.in_use++;
|
|
if (++wq->sq.pidx == wq->sq.size)
|
|
wq->sq.pidx = 0;
|
|
wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
|
|
if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
|
|
wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
|
|
}
|
|
|
|
static inline void t4_sq_consume(struct t4_wq *wq)
|
|
{
|
|
BUG_ON(wq->sq.in_use < 1);
|
|
if (wq->sq.cidx == wq->sq.flush_cidx)
|
|
wq->sq.flush_cidx = -1;
|
|
wq->sq.in_use--;
|
|
if (++wq->sq.cidx == wq->sq.size)
|
|
wq->sq.cidx = 0;
|
|
}
|
|
|
|
static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
|
|
{
|
|
return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
|
|
}
|
|
|
|
static inline u16 t4_sq_wq_size(struct t4_wq *wq)
|
|
{
|
|
return wq->sq.size * T4_SQ_NUM_SLOTS;
|
|
}
|
|
|
|
/* This function copies 64 byte coalesced work request to memory
|
|
* mapped BAR2 space. For coalesced WRs, the SGE fetches data
|
|
* from the FIFO instead of from Host.
|
|
*/
|
|
static inline void pio_copy(u64 __iomem *dst, u64 *src)
|
|
{
|
|
int count = 8;
|
|
|
|
while (count) {
|
|
writeq(*src, dst);
|
|
src++;
|
|
dst++;
|
|
count--;
|
|
}
|
|
}
|
|
|
|
static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
|
|
union t4_wr *wqe)
|
|
{
|
|
|
|
/* Flush host queue memory writes. */
|
|
wmb();
|
|
if (t5) {
|
|
if (inc == 1 && wqe) {
|
|
PDBG("%s: WC wq->sq.pidx = %d\n",
|
|
__func__, wq->sq.pidx);
|
|
pio_copy(wq->sq.udb + 7, (void *)wqe);
|
|
} else {
|
|
PDBG("%s: DB wq->sq.pidx = %d\n",
|
|
__func__, wq->sq.pidx);
|
|
writel(PIDX_T5(inc), wq->sq.udb);
|
|
}
|
|
|
|
/* Flush user doorbell area writes. */
|
|
wmb();
|
|
return;
|
|
}
|
|
writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
|
|
}
|
|
|
|
static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
|
|
union t4_recv_wr *wqe)
|
|
{
|
|
|
|
/* Flush host queue memory writes. */
|
|
wmb();
|
|
if (t5) {
|
|
if (inc == 1 && wqe) {
|
|
PDBG("%s: WC wq->rq.pidx = %d\n",
|
|
__func__, wq->rq.pidx);
|
|
pio_copy(wq->rq.udb + 7, (void *)wqe);
|
|
} else {
|
|
PDBG("%s: DB wq->rq.pidx = %d\n",
|
|
__func__, wq->rq.pidx);
|
|
writel(PIDX_T5(inc), wq->rq.udb);
|
|
}
|
|
|
|
/* Flush user doorbell area writes. */
|
|
wmb();
|
|
return;
|
|
}
|
|
writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
|
|
}
|
|
|
|
static inline int t4_wq_in_error(struct t4_wq *wq)
|
|
{
|
|
return wq->rq.queue[wq->rq.size].status.qp_err;
|
|
}
|
|
|
|
static inline void t4_set_wq_in_error(struct t4_wq *wq)
|
|
{
|
|
wq->rq.queue[wq->rq.size].status.qp_err = 1;
|
|
}
|
|
|
|
static inline void t4_disable_wq_db(struct t4_wq *wq)
|
|
{
|
|
wq->rq.queue[wq->rq.size].status.db_off = 1;
|
|
}
|
|
|
|
static inline void t4_enable_wq_db(struct t4_wq *wq)
|
|
{
|
|
wq->rq.queue[wq->rq.size].status.db_off = 0;
|
|
}
|
|
|
|
static inline int t4_wq_db_enabled(struct t4_wq *wq)
|
|
{
|
|
return !wq->rq.queue[wq->rq.size].status.db_off;
|
|
}
|
|
|
|
struct t4_cq {
|
|
struct t4_cqe *queue;
|
|
dma_addr_t dma_addr;
|
|
DEFINE_DMA_UNMAP_ADDR(mapping);
|
|
struct t4_cqe *sw_queue;
|
|
void __iomem *gts;
|
|
struct c4iw_rdev *rdev;
|
|
u64 ugts;
|
|
size_t memsize;
|
|
__be64 bits_type_ts;
|
|
u32 cqid;
|
|
u16 size; /* including status page */
|
|
u16 cidx;
|
|
u16 sw_pidx;
|
|
u16 sw_cidx;
|
|
u16 sw_in_use;
|
|
u16 cidx_inc;
|
|
u8 gen;
|
|
u8 error;
|
|
};
|
|
|
|
static inline int t4_arm_cq(struct t4_cq *cq, int se)
|
|
{
|
|
u32 val;
|
|
|
|
while (cq->cidx_inc > CIDXINC_MASK) {
|
|
val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
|
|
INGRESSQID(cq->cqid);
|
|
writel(val, cq->gts);
|
|
cq->cidx_inc -= CIDXINC_MASK;
|
|
}
|
|
val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
|
|
INGRESSQID(cq->cqid);
|
|
writel(val, cq->gts);
|
|
cq->cidx_inc = 0;
|
|
return 0;
|
|
}
|
|
|
|
static inline void t4_swcq_produce(struct t4_cq *cq)
|
|
{
|
|
cq->sw_in_use++;
|
|
if (cq->sw_in_use == cq->size) {
|
|
PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
|
|
cq->error = 1;
|
|
BUG_ON(1);
|
|
}
|
|
if (++cq->sw_pidx == cq->size)
|
|
cq->sw_pidx = 0;
|
|
}
|
|
|
|
static inline void t4_swcq_consume(struct t4_cq *cq)
|
|
{
|
|
BUG_ON(cq->sw_in_use < 1);
|
|
cq->sw_in_use--;
|
|
if (++cq->sw_cidx == cq->size)
|
|
cq->sw_cidx = 0;
|
|
}
|
|
|
|
static inline void t4_hwcq_consume(struct t4_cq *cq)
|
|
{
|
|
cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
|
|
if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_MASK) {
|
|
u32 val;
|
|
|
|
val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |
|
|
INGRESSQID(cq->cqid);
|
|
writel(val, cq->gts);
|
|
cq->cidx_inc = 0;
|
|
}
|
|
if (++cq->cidx == cq->size) {
|
|
cq->cidx = 0;
|
|
cq->gen ^= 1;
|
|
}
|
|
}
|
|
|
|
static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
|
|
{
|
|
return (CQE_GENBIT(cqe) == cq->gen);
|
|
}
|
|
|
|
static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
|
|
{
|
|
int ret;
|
|
u16 prev_cidx;
|
|
|
|
if (cq->cidx == 0)
|
|
prev_cidx = cq->size - 1;
|
|
else
|
|
prev_cidx = cq->cidx - 1;
|
|
|
|
if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
|
|
ret = -EOVERFLOW;
|
|
cq->error = 1;
|
|
printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
|
|
BUG_ON(1);
|
|
} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
|
|
|
|
/* Ensure CQE is flushed to memory */
|
|
rmb();
|
|
*cqe = &cq->queue[cq->cidx];
|
|
ret = 0;
|
|
} else
|
|
ret = -ENODATA;
|
|
return ret;
|
|
}
|
|
|
|
static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
|
|
{
|
|
if (cq->sw_in_use == cq->size) {
|
|
PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
|
|
cq->error = 1;
|
|
BUG_ON(1);
|
|
return NULL;
|
|
}
|
|
if (cq->sw_in_use)
|
|
return &cq->sw_queue[cq->sw_cidx];
|
|
return NULL;
|
|
}
|
|
|
|
static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (cq->error)
|
|
ret = -ENODATA;
|
|
else if (cq->sw_in_use)
|
|
*cqe = &cq->sw_queue[cq->sw_cidx];
|
|
else
|
|
ret = t4_next_hw_cqe(cq, cqe);
|
|
return ret;
|
|
}
|
|
|
|
static inline int t4_cq_in_error(struct t4_cq *cq)
|
|
{
|
|
return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
|
|
}
|
|
|
|
static inline void t4_set_cq_in_error(struct t4_cq *cq)
|
|
{
|
|
((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
|
|
}
|
|
#endif
|
|
|
|
struct t4_dev_status_page {
|
|
u8 db_off;
|
|
};
|