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e1e3e7008a
Chapter 57.7.5 of SAM9X60 datasheet specifies that the maximum drift of
this oscillator is +- 3KHz. Use that value and the formula at [1]
or the calculator at [2] to compute the PPB value.
[1] https://www.everythingrf.com/rf-calculators/ppm-to-hz-calculator
[2] https://www.changpuak.ch/electronics/ppm_to_Hz_converter.php
Fixes: 04bcc4275e ("clk: at91: sckc: add support for SAM9X60")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
634 lines
14 KiB
C
634 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* drivers/clk/at91/sckc.c
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#define SLOW_CLOCK_FREQ 32768
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#define SLOWCK_SW_CYCLES 5
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#define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
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SLOW_CLOCK_FREQ)
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#define AT91_SCKC_CR 0x00
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struct clk_slow_bits {
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u32 cr_rcen;
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u32 cr_osc32en;
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u32 cr_osc32byp;
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u32 cr_oscsel;
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};
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struct clk_slow_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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const struct clk_slow_bits *bits;
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unsigned long startup_usec;
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};
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#define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw)
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struct clk_sama5d4_slow_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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const struct clk_slow_bits *bits;
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unsigned long startup_usec;
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bool prepared;
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};
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#define to_clk_sama5d4_slow_osc(hw) container_of(hw, struct clk_sama5d4_slow_osc, hw)
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struct clk_slow_rc_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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const struct clk_slow_bits *bits;
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unsigned long frequency;
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unsigned long accuracy;
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unsigned long startup_usec;
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};
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#define to_clk_slow_rc_osc(hw) container_of(hw, struct clk_slow_rc_osc, hw)
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struct clk_sam9x5_slow {
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struct clk_hw hw;
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void __iomem *sckcr;
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const struct clk_slow_bits *bits;
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u8 parent;
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};
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#define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
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static int clk_slow_osc_prepare(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en))
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return 0;
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writel(tmp | osc->bits->cr_osc32en, sckcr);
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if (system_state < SYSTEM_RUNNING)
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udelay(osc->startup_usec);
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else
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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return 0;
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}
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static void clk_slow_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & osc->bits->cr_osc32byp)
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return;
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writel(tmp & ~osc->bits->cr_osc32en, sckcr);
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}
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static int clk_slow_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & osc->bits->cr_osc32byp)
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return 1;
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return !!(tmp & osc->bits->cr_osc32en);
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}
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static const struct clk_ops slow_osc_ops = {
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.prepare = clk_slow_osc_prepare,
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.unprepare = clk_slow_osc_unprepare,
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.is_prepared = clk_slow_osc_is_prepared,
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};
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static struct clk_hw * __init
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at91_clk_register_slow_osc(void __iomem *sckcr,
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const char *name,
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const char *parent_name,
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unsigned long startup,
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bool bypass,
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const struct clk_slow_bits *bits)
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{
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struct clk_slow_osc *osc;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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if (!sckcr || !name || !parent_name)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &slow_osc_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->sckcr = sckcr;
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osc->startup_usec = startup;
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osc->bits = bits;
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if (bypass)
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writel((readl(sckcr) & ~osc->bits->cr_osc32en) |
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osc->bits->cr_osc32byp, sckcr);
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hw = &osc->hw;
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ret = clk_hw_register(NULL, &osc->hw);
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if (ret) {
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kfree(osc);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void at91_clk_unregister_slow_osc(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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clk_hw_unregister(hw);
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kfree(osc);
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}
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static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return osc->frequency;
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}
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static unsigned long clk_slow_rc_osc_recalc_accuracy(struct clk_hw *hw,
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unsigned long parent_acc)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return osc->accuracy;
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}
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static int clk_slow_rc_osc_prepare(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);
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if (system_state < SYSTEM_RUNNING)
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udelay(osc->startup_usec);
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else
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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return 0;
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}
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static void clk_slow_rc_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr);
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}
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static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return !!(readl(osc->sckcr) & osc->bits->cr_rcen);
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}
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static const struct clk_ops slow_rc_osc_ops = {
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.prepare = clk_slow_rc_osc_prepare,
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.unprepare = clk_slow_rc_osc_unprepare,
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.is_prepared = clk_slow_rc_osc_is_prepared,
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.recalc_rate = clk_slow_rc_osc_recalc_rate,
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.recalc_accuracy = clk_slow_rc_osc_recalc_accuracy,
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};
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static struct clk_hw * __init
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at91_clk_register_slow_rc_osc(void __iomem *sckcr,
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const char *name,
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unsigned long frequency,
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unsigned long accuracy,
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unsigned long startup,
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const struct clk_slow_bits *bits)
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{
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struct clk_slow_rc_osc *osc;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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if (!sckcr || !name)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &slow_rc_osc_ops;
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init.parent_names = NULL;
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init.num_parents = 0;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->sckcr = sckcr;
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osc->bits = bits;
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osc->frequency = frequency;
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osc->accuracy = accuracy;
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osc->startup_usec = startup;
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hw = &osc->hw;
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ret = clk_hw_register(NULL, &osc->hw);
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if (ret) {
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kfree(osc);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void at91_clk_unregister_slow_rc_osc(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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clk_hw_unregister(hw);
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kfree(osc);
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}
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static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
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void __iomem *sckcr = slowck->sckcr;
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u32 tmp;
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if (index > 1)
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return -EINVAL;
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tmp = readl(sckcr);
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if ((!index && !(tmp & slowck->bits->cr_oscsel)) ||
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(index && (tmp & slowck->bits->cr_oscsel)))
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return 0;
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if (index)
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tmp |= slowck->bits->cr_oscsel;
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else
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tmp &= ~slowck->bits->cr_oscsel;
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writel(tmp, sckcr);
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if (system_state < SYSTEM_RUNNING)
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udelay(SLOWCK_SW_TIME_USEC);
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else
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usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
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return 0;
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}
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static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
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{
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struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
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return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel);
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}
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static const struct clk_ops sam9x5_slow_ops = {
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.set_parent = clk_sam9x5_slow_set_parent,
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.get_parent = clk_sam9x5_slow_get_parent,
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};
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static struct clk_hw * __init
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at91_clk_register_sam9x5_slow(void __iomem *sckcr,
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const char *name,
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const char **parent_names,
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int num_parents,
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const struct clk_slow_bits *bits)
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{
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struct clk_sam9x5_slow *slowck;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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if (!sckcr || !name || !parent_names || !num_parents)
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return ERR_PTR(-EINVAL);
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slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
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if (!slowck)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &sam9x5_slow_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = 0;
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slowck->hw.init = &init;
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slowck->sckcr = sckcr;
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slowck->bits = bits;
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slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel);
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hw = &slowck->hw;
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ret = clk_hw_register(NULL, &slowck->hw);
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if (ret) {
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kfree(slowck);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void at91_clk_unregister_sam9x5_slow(struct clk_hw *hw)
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{
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struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
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clk_hw_unregister(hw);
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kfree(slowck);
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}
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static void __init at91sam9x5_sckc_register(struct device_node *np,
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unsigned int rc_osc_startup_us,
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const struct clk_slow_bits *bits)
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{
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const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
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void __iomem *regbase = of_iomap(np, 0);
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struct device_node *child = NULL;
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const char *xtal_name;
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struct clk_hw *slow_rc, *slow_osc, *slowck;
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bool bypass;
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int ret;
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if (!regbase)
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return;
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slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0],
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32768, 50000000,
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rc_osc_startup_us, bits);
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if (IS_ERR(slow_rc))
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return;
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xtal_name = of_clk_get_parent_name(np, 0);
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if (!xtal_name) {
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/* DT backward compatibility */
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child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc");
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if (!child)
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goto unregister_slow_rc;
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xtal_name = of_clk_get_parent_name(child, 0);
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bypass = of_property_read_bool(child, "atmel,osc-bypass");
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child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow");
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} else {
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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}
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if (!xtal_name)
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goto unregister_slow_rc;
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slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
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xtal_name, 1200000, bypass, bits);
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if (IS_ERR(slow_osc))
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goto unregister_slow_rc;
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slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names,
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2, bits);
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if (IS_ERR(slowck))
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goto unregister_slow_osc;
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/* DT backward compatibility */
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if (child)
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ret = of_clk_add_hw_provider(child, of_clk_hw_simple_get,
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slowck);
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else
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ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);
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if (WARN_ON(ret))
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goto unregister_slowck;
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return;
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unregister_slowck:
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at91_clk_unregister_sam9x5_slow(slowck);
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unregister_slow_osc:
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at91_clk_unregister_slow_osc(slow_osc);
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unregister_slow_rc:
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at91_clk_unregister_slow_rc_osc(slow_rc);
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}
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static const struct clk_slow_bits at91sam9x5_bits = {
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.cr_rcen = BIT(0),
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.cr_osc32en = BIT(1),
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.cr_osc32byp = BIT(2),
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.cr_oscsel = BIT(3),
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};
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static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
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{
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at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
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of_at91sam9x5_sckc_setup);
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static void __init of_sama5d3_sckc_setup(struct device_node *np)
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{
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at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits);
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}
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CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc",
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of_sama5d3_sckc_setup);
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static const struct clk_slow_bits at91sam9x60_bits = {
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.cr_osc32en = BIT(1),
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.cr_osc32byp = BIT(2),
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.cr_oscsel = BIT(24),
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};
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static void __init of_sam9x60_sckc_setup(struct device_node *np)
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{
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void __iomem *regbase = of_iomap(np, 0);
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struct clk_hw_onecell_data *clk_data;
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struct clk_hw *slow_rc, *slow_osc;
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const char *xtal_name;
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const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
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bool bypass;
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int ret;
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if (!regbase)
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return;
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slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
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NULL, 0, 32768,
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93750000);
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if (IS_ERR(slow_rc))
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return;
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xtal_name = of_clk_get_parent_name(np, 0);
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if (!xtal_name)
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goto unregister_slow_rc;
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
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xtal_name, 5000000, bypass,
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&at91sam9x60_bits);
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if (IS_ERR(slow_osc))
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goto unregister_slow_rc;
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clk_data = kzalloc(struct_size(clk_data, hws, 2), GFP_KERNEL);
|
|
if (!clk_data)
|
|
goto unregister_slow_osc;
|
|
|
|
/* MD_SLCK and TD_SLCK. */
|
|
clk_data->num = 2;
|
|
clk_data->hws[0] = clk_hw_register_fixed_rate(NULL, "md_slck",
|
|
parent_names[0],
|
|
0, 32768);
|
|
if (IS_ERR(clk_data->hws[0]))
|
|
goto clk_data_free;
|
|
|
|
clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",
|
|
parent_names, 2,
|
|
&at91sam9x60_bits);
|
|
if (IS_ERR(clk_data->hws[1]))
|
|
goto unregister_md_slck;
|
|
|
|
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
|
if (WARN_ON(ret))
|
|
goto unregister_td_slck;
|
|
|
|
return;
|
|
|
|
unregister_td_slck:
|
|
at91_clk_unregister_sam9x5_slow(clk_data->hws[1]);
|
|
unregister_md_slck:
|
|
clk_hw_unregister(clk_data->hws[0]);
|
|
clk_data_free:
|
|
kfree(clk_data);
|
|
unregister_slow_osc:
|
|
at91_clk_unregister_slow_osc(slow_osc);
|
|
unregister_slow_rc:
|
|
clk_hw_unregister(slow_rc);
|
|
}
|
|
CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc",
|
|
of_sam9x60_sckc_setup);
|
|
|
|
static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
|
|
{
|
|
struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
|
|
|
|
if (osc->prepared)
|
|
return 0;
|
|
|
|
/*
|
|
* Assume that if it has already been selected (for example by the
|
|
* bootloader), enough time has aready passed.
|
|
*/
|
|
if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {
|
|
osc->prepared = true;
|
|
return 0;
|
|
}
|
|
|
|
if (system_state < SYSTEM_RUNNING)
|
|
udelay(osc->startup_usec);
|
|
else
|
|
usleep_range(osc->startup_usec, osc->startup_usec + 1);
|
|
osc->prepared = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int clk_sama5d4_slow_osc_is_prepared(struct clk_hw *hw)
|
|
{
|
|
struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
|
|
|
|
return osc->prepared;
|
|
}
|
|
|
|
static const struct clk_ops sama5d4_slow_osc_ops = {
|
|
.prepare = clk_sama5d4_slow_osc_prepare,
|
|
.is_prepared = clk_sama5d4_slow_osc_is_prepared,
|
|
};
|
|
|
|
static const struct clk_slow_bits at91sama5d4_bits = {
|
|
.cr_oscsel = BIT(3),
|
|
};
|
|
|
|
static void __init of_sama5d4_sckc_setup(struct device_node *np)
|
|
{
|
|
void __iomem *regbase = of_iomap(np, 0);
|
|
struct clk_hw *slow_rc, *slowck;
|
|
struct clk_sama5d4_slow_osc *osc;
|
|
struct clk_init_data init;
|
|
const char *xtal_name;
|
|
const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
|
|
int ret;
|
|
|
|
if (!regbase)
|
|
return;
|
|
|
|
slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL,
|
|
parent_names[0],
|
|
NULL, 0, 32768,
|
|
250000000);
|
|
if (IS_ERR(slow_rc))
|
|
return;
|
|
|
|
xtal_name = of_clk_get_parent_name(np, 0);
|
|
|
|
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
|
|
if (!osc)
|
|
goto unregister_slow_rc;
|
|
|
|
init.name = parent_names[1];
|
|
init.ops = &sama5d4_slow_osc_ops;
|
|
init.parent_names = &xtal_name;
|
|
init.num_parents = 1;
|
|
init.flags = CLK_IGNORE_UNUSED;
|
|
|
|
osc->hw.init = &init;
|
|
osc->sckcr = regbase;
|
|
osc->startup_usec = 1200000;
|
|
osc->bits = &at91sama5d4_bits;
|
|
|
|
ret = clk_hw_register(NULL, &osc->hw);
|
|
if (ret)
|
|
goto free_slow_osc_data;
|
|
|
|
slowck = at91_clk_register_sam9x5_slow(regbase, "slowck",
|
|
parent_names, 2,
|
|
&at91sama5d4_bits);
|
|
if (IS_ERR(slowck))
|
|
goto unregister_slow_osc;
|
|
|
|
ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);
|
|
if (WARN_ON(ret))
|
|
goto unregister_slowck;
|
|
|
|
return;
|
|
|
|
unregister_slowck:
|
|
at91_clk_unregister_sam9x5_slow(slowck);
|
|
unregister_slow_osc:
|
|
clk_hw_unregister(&osc->hw);
|
|
free_slow_osc_data:
|
|
kfree(osc);
|
|
unregister_slow_rc:
|
|
clk_hw_unregister(slow_rc);
|
|
}
|
|
CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",
|
|
of_sama5d4_sckc_setup);
|