mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-21 10:05:00 +08:00
27e154b2b6
Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed
in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
Hardware User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
49 lines
1.4 KiB
C
49 lines
1.4 KiB
C
/*
|
|
* Copyright (C) 2015 Renesas Electronics Corp.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*/
|
|
|
|
#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
|
|
#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
|
|
|
|
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
|
|
|
/* r8a7791 CPG Core Clocks */
|
|
#define R8A7791_CLK_Z 0
|
|
#define R8A7791_CLK_ZG 1
|
|
#define R8A7791_CLK_ZTR 2
|
|
#define R8A7791_CLK_ZTRD2 3
|
|
#define R8A7791_CLK_ZT 4
|
|
#define R8A7791_CLK_ZX 5
|
|
#define R8A7791_CLK_ZS 6
|
|
#define R8A7791_CLK_HP 7
|
|
#define R8A7791_CLK_I 8
|
|
#define R8A7791_CLK_B 9
|
|
#define R8A7791_CLK_LB 10
|
|
#define R8A7791_CLK_P 11
|
|
#define R8A7791_CLK_CL 12
|
|
#define R8A7791_CLK_M2 13
|
|
#define R8A7791_CLK_ADSP 14
|
|
#define R8A7791_CLK_ZB3 15
|
|
#define R8A7791_CLK_ZB3D2 16
|
|
#define R8A7791_CLK_DDR 17
|
|
#define R8A7791_CLK_SDH 18
|
|
#define R8A7791_CLK_SD0 19
|
|
#define R8A7791_CLK_SD2 20
|
|
#define R8A7791_CLK_SD3 21
|
|
#define R8A7791_CLK_MMC0 22
|
|
#define R8A7791_CLK_MP 23
|
|
#define R8A7791_CLK_SSP 24
|
|
#define R8A7791_CLK_SSPRS 25
|
|
#define R8A7791_CLK_QSPI 26
|
|
#define R8A7791_CLK_CP 27
|
|
#define R8A7791_CLK_RCAN 28
|
|
#define R8A7791_CLK_R 29
|
|
#define R8A7791_CLK_OSC 30
|
|
|
|
#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
|